///
virtual const X86RegisterInfo &getRegisterInfo() const { return RI; }
- // Return true if the instruction is a register to register move and
- // leave the source and dest operands in the passed parameters.
- //
- bool isMoveInstr(const MachineInstr& MI, unsigned& sourceReg,
- unsigned& destReg) const;
+ /// Return true if the instruction is a register to register move and return
+ /// the source and dest operands and their sub-register indices by reference.
+ virtual bool isMoveInstr(const MachineInstr &MI,
+ unsigned &SrcReg, unsigned &DstReg,
+ unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
+
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;
virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
- SmallVectorImpl<MachineOperand> &Cond) const;
+ SmallVectorImpl<MachineOperand> &Cond,
+ bool AllowModify) const;
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
virtual
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
- /// IgnoreRegisterClassBarriers - Returns true if pre-register allocation
- /// live interval splitting pass should ignore barriers of the specified
- /// register class.
- bool IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const;
-
- const TargetRegisterClass *getPointerRegClass() const;
+ /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
+ /// instruction that defines the specified register class.
+ bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
// specified machine instruction.