Fix JIT encoding bugs for shift / rotate by one ops.

[oota-llvm.git] / lib / Target / X86 / X86InstrX86-64.td

diff --git a/lib/Target/X86/X86InstrX86-64.td b/lib/Target/X86/X86InstrX86-64.td
index ea07e6d5898a56f12afb73577aecc0946db56486..0e024d1931e5e786e640f2a897d2d7001407cf8c 100644 (file)
--- a/lib/Target/X86/X86InstrX86-64.td
+++ b/lib/Target/X86/X86InstrX86-64.td
@@ -24,13 +24,11 @@ def i64i8imm   : Operand<i64>;
 
 def lea64mem : Operand<i64> {
   let PrintMethod = "printi64mem";
-  let NumMIOperands = 4;
   let MIOperandInfo = (ops GR64, i8imm, GR64, i32imm);
 }
 
 def lea64_32mem : Operand<i32> {
   let PrintMethod = "printlea64_32mem";
-  let NumMIOperands = 4;
   let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
 }
 
@@ -38,7 +36,7 @@ def lea64_32mem : Operand<i32> {
 // Complex Pattern Definitions...
 //
 def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
-                               [add, mul, shl, or, frameindex, X86Wrapper]>;
+                               [add, mul, shl, or, frameindex, X86Wrapper], []>;
 
 //===----------------------------------------------------------------------===//
 // Instruction templates...
@@ -61,6 +59,8 @@ class RSSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
       : SSI<o, F, ops, asm, pattern>, REX_W;
 class RSDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
       : SDI<o, F, ops, asm, pattern>, REX_W;
+class RPDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
+      : PDI<o, F, ops, asm, pattern>, REX_W;
 
 //===----------------------------------------------------------------------===//
 // Pattern fragments...
@@ -84,20 +84,20 @@ def i64immSExt8  : PatLeaf<(i64 imm), [{
   return (int64_t)N->getValue() == (int8_t)N->getValue();
 }]>;
 
-def sextloadi64i1  : PatFrag<(ops node:$ptr), (i64 (sextload node:$ptr, i1))>;
-def sextloadi64i8  : PatFrag<(ops node:$ptr), (i64 (sextload node:$ptr, i8))>;
-def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextload node:$ptr, i16))>;
-def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextload node:$ptr, i32))>;
+def sextloadi64i1  : PatFrag<(ops node:$ptr), (i64 (sextloadi1 node:$ptr))>;
+def sextloadi64i8  : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
+def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
+def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
 
-def zextloadi64i1  : PatFrag<(ops node:$ptr), (i64 (zextload node:$ptr, i1))>;
-def zextloadi64i8  : PatFrag<(ops node:$ptr), (i64 (zextload node:$ptr, i8))>;
-def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextload node:$ptr, i16))>;
-def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextload node:$ptr, i32))>;
+def zextloadi64i1  : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
+def zextloadi64i8  : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
+def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
+def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
 
-def extloadi64i1   : PatFrag<(ops node:$ptr), (i64 (extload node:$ptr, i1))>;
-def extloadi64i8   : PatFrag<(ops node:$ptr), (i64 (extload node:$ptr, i8))>;
-def extloadi64i16  : PatFrag<(ops node:$ptr), (i64 (extload node:$ptr, i16))>;
-def extloadi64i32  : PatFrag<(ops node:$ptr), (i64 (extload node:$ptr, i32))>;
+def extloadi64i1   : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
+def extloadi64i8   : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
+def extloadi64i16  : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
+def extloadi64i32  : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
 
 //===----------------------------------------------------------------------===//
 // Instruction list...
@@ -466,7 +466,7 @@ def SHL64mCL : RI<0xD3, MRM4m, (ops i64mem:$dst),
 def SHL64mi : RIi8<0xC1, MRM4m, (ops i64mem:$dst, i8imm:$src),
                   "shl{q} {$src, $dst|$dst, $src}",
                  [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
-def SHL64m1 : RI<0xC1, MRM4m, (ops i64mem:$dst),
+def SHL64m1 : RI<0xD1, MRM4m, (ops i64mem:$dst),
                   "shl{q} $dst",
                  [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
 
@@ -490,7 +490,7 @@ def SHR64mCL : RI<0xD3, MRM5m, (ops i64mem:$dst),
 def SHR64mi : RIi8<0xC1, MRM5m, (ops i64mem:$dst, i8imm:$src),
                   "shr{q} {$src, $dst|$dst, $src}",
                  [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
-def SHR64m1 : RI<0xC1, MRM5m, (ops i64mem:$dst),
+def SHR64m1 : RI<0xD1, MRM5m, (ops i64mem:$dst),
                   "shr{q} $dst",
                  [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
 
@@ -513,7 +513,7 @@ def SAR64mCL : RI<0xD3, MRM7m, (ops i64mem:$dst),
 def SAR64mi  : RIi8<0xC1, MRM7m, (ops i64mem:$dst, i8imm:$src),
                     "sar{q} {$src, $dst|$dst, $src}",
                  [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
-def SAR64m1 : RI<0xC1, MRM7m, (ops i64mem:$dst),
+def SAR64m1 : RI<0xD1, MRM7m, (ops i64mem:$dst),
                   "sar{q} $dst",
                  [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
 
@@ -525,7 +525,7 @@ def ROL64rCL : RI<0xD3, MRM0r, (ops GR64:$dst, GR64:$src),
 def ROL64ri  : RIi8<0xC1, MRM0r, (ops GR64:$dst, GR64:$src1, i8imm:$src2),
                     "rol{q} {$src2, $dst|$dst, $src2}",
                     [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
-def ROL64r1  : RI<0xC1, MRM0r, (ops GR64:$dst, GR64:$src1),
+def ROL64r1  : RI<0xD1, MRM0r, (ops GR64:$dst, GR64:$src1),
                   "rol{q} $dst",
                   [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
 } // isTwoAddress
@@ -548,7 +548,7 @@ def ROR64rCL : RI<0xD3, MRM1r, (ops GR64:$dst, GR64:$src),
 def ROR64ri  : RIi8<0xC1, MRM1r, (ops GR64:$dst, GR64:$src1, i8imm:$src2),
                     "ror{q} {$src2, $dst|$dst, $src2}",
                     [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
-def ROR64r1  : RI<0xC1, MRM1r, (ops GR64:$dst, GR64:$src1),
+def ROR64r1  : RI<0xD1, MRM1r, (ops GR64:$dst, GR64:$src1),
                   "ror{q} $dst",
                   [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
 } // isTwoAddress
@@ -711,14 +711,13 @@ def TEST64rr : RI<0x85, MRMDestReg, (ops GR64:$src1, GR64:$src2),
                   [(X86cmp (and GR64:$src1, GR64:$src2), 0)]>;
 def TEST64rm : RI<0x85, MRMSrcMem, (ops GR64:$src1, i64mem:$src2),
                   "test{q} {$src2, $src1|$src1, $src2}",
-                  [/*(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0)*/]>;
+                  [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0)]>;
 def TEST64ri32 : RIi32<0xF7, MRM0r, (ops GR64:$src1, i64i32imm:$src2),
                        "test{q} {$src2, $src1|$src1, $src2}",
                        [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0)]>;
 def TEST64mi32 : RIi32<0xF7, MRM0m, (ops i64mem:$src1, i64i32imm:$src2),
                        "test{q} {$src2, $src1|$src1, $src2}",
-                      [/*(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2),
-                         0)*/]>;
+                  [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0)]>;
 
 def CMP64rr : RI<0x39, MRMDestReg, (ops GR64:$src1, GR64:$src2),
                  "cmp{q} {$src2, $src1|$src1, $src2}",
@@ -1079,3 +1078,27 @@ def : Pat<(or (shl GR64:$src1, CL:$amt),
 def : Pat<(store (or (shl (loadi64 addr:$dst), CL:$amt),
                      (srl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
           (SHLD64mrCL addr:$dst, GR64:$src2)>;
+
+//===----------------------------------------------------------------------===//
+// X86-64 SSE Instructions
+//===----------------------------------------------------------------------===//
+
+// Move instructions...
+
+def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (ops VR128:$dst, GR64:$src),
+                        "movq {$src, $dst|$dst, $src}",
+                        [(set VR128:$dst,
+                          (v2i64 (scalar_to_vector GR64:$src)))]>;
+def MOV64toPQIrm : RPDI<0x6E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
+                        "movq {$src, $dst|$dst, $src}",
+                        [(set VR128:$dst,
+                          (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>;
+
+def MOVPQIto64rr  : RPDI<0x7E, MRMDestReg, (ops GR64:$dst, VR128:$src),
+                         "movd {$src, $dst|$dst, $src}",
+                         [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
+                                           (iPTR 0)))]>;
+def MOVPQIto64mr  : RPDI<0x7E, MRMDestMem, (ops i64mem:$dst, VR128:$src),
+                         "movd {$src, $dst|$dst, $src}",
+                         [(store (i64 (vector_extract (v2i64 VR128:$src),
+                                       (iPTR 0))), addr:$dst)]>;