//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
SwitchToTextSection(getSectionForFunction(*F).c_str(), F);
+ unsigned FnAlign = OptimizeForSize ? 1 : 4;
switch (F->getLinkage()) {
default: assert(0 && "Unsupported linkage type!");
case Function::InternalLinkage:
- EmitAlignment(4);
+ EmitAlignment(FnAlign);
break;
case Function::DLLExportLinkage:
DLLExportedFns.insert(CurrentFnName);
//FALLS THROUGH
case Function::ExternalLinkage:
O << "\tpublic " << CurrentFnName << "\n";
- EmitAlignment(4);
+ EmitAlignment(FnAlign);
break;
}
I != E; ++I) {
// Print a label for the basic block if there are any predecessors.
if (!I->pred_empty()) {
- printBasicBlockLabel(I, true);
+ printBasicBlockLabel(I, true, true);
O << '\n';
}
for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
II != E; ++II) {
// Print the assembly for the instruction.
- O << "\t";
printMachineInstruction(II);
}
}
}
void X86IntelAsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op) {
- unsigned char value = MI->getOperand(Op).getImmedValue();
+ unsigned char value = MI->getOperand(Op).getImm();
assert(value <= 7 && "Invalid ssecc argument!");
switch (value) {
case 0: O << "eq"; break;
void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
const char *Modifier) {
- const MRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) {
case MachineOperand::MO_Register: {
- if (MRegisterInfo::isPhysicalRegister(MO.getReg())) {
+ if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
unsigned Reg = MO.getReg();
if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
- MVT::ValueType VT = (strcmp(Modifier,"subreg64") == 0) ?
+ MVT VT = (strcmp(Modifier,"subreg64") == 0) ?
MVT::i64 : ((strcmp(Modifier, "subreg32") == 0) ? MVT::i32 :
((strcmp(Modifier,"subreg16") == 0) ? MVT::i16 :MVT::i8));
Reg = getX86SubSuperRegister(Reg, VT);
}
- O << RI.get(Reg).Name;
+ O << TRI->getAsmName(Reg);
} else
O << "reg" << MO.getReg();
return;
}
case MachineOperand::MO_Immediate:
- O << MO.getImmedValue();
+ O << MO.getImm();
return;
case MachineOperand::MO_MachineBasicBlock:
- printBasicBlockLabel(MO.getMachineBasicBlock());
+ printBasicBlockLabel(MO.getMBB());
return;
case MachineOperand::MO_JumpTableIndex: {
bool isMemOp = Modifier && !strcmp(Modifier, "mem");
if (!isMemOp) O << "OFFSET ";
- O << TAI->getPrivateGlobalPrefix() << "JTI" << MO.getJumpTableIndex()
- << '_' << CurrentFnName;
+ O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
+ << "_" << MO.getIndex();
return;
}
case MachineOperand::MO_ConstantPoolIndex: {
bool isMemOp = Modifier && !strcmp(Modifier, "mem");
if (!isMemOp) O << "OFFSET ";
O << "[" << TAI->getPrivateGlobalPrefix() << "CPI"
- << MO.getConstantPoolIndex() << '_' << CurrentFnName;
+ << getFunctionNumber() << "_" << MO.getIndex();
int Offset = MO.getOffset();
if (Offset > 0)
O << " + " << Offset;
assert(isMem(MI, Op) && "Invalid memory reference!");
const MachineOperand &BaseReg = MI->getOperand(Op);
- int ScaleVal = MI->getOperand(Op+1).getImmedValue();
+ int ScaleVal = MI->getOperand(Op+1).getImm();
const MachineOperand &IndexReg = MI->getOperand(Op+2);
const MachineOperand &DispSpec = MI->getOperand(Op+3);
O << " + ";
printOp(DispSpec, "mem");
} else {
- int DispVal = DispSpec.getImmedValue();
+ int DispVal = DispSpec.getImm();
if (DispVal || (!BaseReg.getReg() && !IndexReg.getReg())) {
- if (NeedPlus)
+ if (NeedPlus) {
if (DispVal > 0)
O << " + ";
else {
O << " - ";
DispVal = -DispVal;
}
+ }
O << DispVal;
}
}
O << "]";
}
+void X86IntelAsmPrinter::printPICJumpTableSetLabel(unsigned uid,
+ const MachineBasicBlock *MBB) const {
+ if (!TAI->getSetDirective())
+ return;
+
+ O << TAI->getSetDirective() << ' ' << TAI->getPrivateGlobalPrefix()
+ << getFunctionNumber() << '_' << uid << "_set_" << MBB->getNumber() << ',';
+ printBasicBlockLabel(MBB, false, false, false);
+ O << '-' << "\"L" << getFunctionNumber() << "$pb\"'\n";
+}
+
void X86IntelAsmPrinter::printPICLabel(const MachineInstr *MI, unsigned Op) {
- O << "\"L" "pb$" << CurrentFnName << "\"\n";
- O << "\"L" "pb$" << CurrentFnName << "\":";
+ O << "\"L" << getFunctionNumber() << "$pb\"\n";
+ O << "\"L" << getFunctionNumber() << "$pb\":";
}
bool X86IntelAsmPrinter::printAsmMRegister(const MachineOperand &MO,
const char Mode) {
- const MRegisterInfo &RI = *TM.getRegisterInfo();
unsigned Reg = MO.getReg();
switch (Mode) {
default: return true; // Unknown mode.
break;
}
- O << '%' << RI.get(Reg).Name;
+ O << '%' << TRI->getAsmName(Reg);
return false;
}
void X86IntelAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
++EmittedInsts;
- // See if a truncate instruction can be turned into a nop.
- switch (MI->getOpcode()) {
- default: break;
- case X86::PsMOVZX64rr32:
- O << TAI->getCommentString() << " ZERO-EXTEND " << "\n\t";
- break;
- }
-
// Call the autogenerated instruction printer routines.
printInstruction(MI);
}
bool bCustomSegment = false;
switch (I->getLinkage()) {
+ case GlobalValue::CommonLinkage:
case GlobalValue::LinkOnceLinkage:
case GlobalValue::WeakLinkage:
SwitchToDataSection("");