Disable this peephole for now. We can't keep track of the fact that the immediate...

[oota-llvm.git] / lib / Target / X86 / X86PeepholeOpt.cpp

diff --git a/lib/Target/X86/X86PeepholeOpt.cpp b/lib/Target/X86/X86PeepholeOpt.cpp
index 512a72136693ca24ee1d59f6192fc3b5a845eccc..fd31d6d0d43bebf0ac6f1bec2a446be3e7c49b6f 100644 (file)
--- a/lib/Target/X86/X86PeepholeOpt.cpp
+++ b/lib/Target/X86/X86PeepholeOpt.cpp
@@ -93,6 +93,7 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
     }
     return false;
 
+#if 0
   case X86::IMULrmi16: case X86::IMULrmi32:
     assert(MI->getNumOperands() == 6 && "These should all have 6 operands!");
     if (MI->getOperand(5).isImmediate()) {
@@ -109,14 +110,15 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
         unsigned R1 = MI->getOperand(1).getReg();
         unsigned Scale = MI->getOperand(2).getImmedValue();
         unsigned R2 = MI->getOperand(3).getReg();
-        unsigned Offset = MI->getOperand(3).getImmedValue();
+        unsigned Offset = MI->getOperand(4).getImmedValue();
         I = MBB.insert(MBB.erase(I),
-                       BuildMI(Opcode, 2, R0).addReg(R1).addZImm(Scale).
+                       BuildMI(Opcode, 5, R0).addReg(R1).addZImm(Scale).
                              addReg(R2).addSImm(Offset).addZImm((char)Val));
         return true;
       }
     }
     return false;
+#endif
 
   case X86::ADDri16:  case X86::ADDri32:
   case X86::ADDmi16:  case X86::ADDmi32:
@@ -153,10 +155,35 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
     }
     return false;
 
+
+  case X86::ANDmi16:  case X86::ANDmi32:
+    assert(MI->getNumOperands() == 5 && "These should all have 5 operands!");
+    if (MI->getOperand(4).isImmediate()) {
+      int Val = MI->getOperand(4).getImmedValue();
+      // If the value is the same when signed extended from 8 bits...
+      if (Val == (signed int)(signed char)Val) {
+        unsigned Opcode;
+        switch (MI->getOpcode()) {
+        default: assert(0 && "Unknown opcode value!");
+        case X86::ANDmi16:  Opcode = X86::ANDmi16b; break;
+        case X86::ANDmi32:  Opcode = X86::ANDmi32b; break;
+        }
+        unsigned R0 = MI->getOperand(0).getReg();
+        unsigned Scale = MI->getOperand(1).getImmedValue();
+        unsigned R1 = MI->getOperand(2).getReg();
+        unsigned Offset = MI->getOperand(3).getImmedValue();
+        I = MBB.insert(MBB.erase(I),
+                       BuildMI(Opcode, 5).addReg(R0).addZImm(Scale).
+                             addReg(R1).addSImm(Offset).addZImm((char)Val));
+        return true;
+      }
+    }
+    return false;
+
 #if 0
-  case X86::MOVir32: Size++;
-  case X86::MOVir16: Size++;
-  case X86::MOVir8:
+  case X86::MOVri32: Size++;
+  case X86::MOVri16: Size++;
+  case X86::MOVri8:
     // FIXME: We can only do this transformation if we know that flags are not
     // used here, because XOR clobbers the flags!
     if (MI->getOperand(1).isImmediate()) {         // avoid mov EAX, <value>
@@ -348,7 +375,7 @@ bool SSAPH::OptimizeAddress(MachineInstr *MI, unsigned OpNo) {
   // Attempt to fold instructions used by the base register into the instruction
   if (MachineInstr *DefInst = getDefiningInst(BaseRegOp)) {
     switch (DefInst->getOpcode()) {
-    case X86::MOVir32:
+    case X86::MOVri32:
       // If there is no displacement set for this instruction set one now.
       // FIXME: If we can fold two immediates together, we should do so!
       if (DisplacementOp.isImmediate() && !DisplacementOp.getImmedValue()) {
@@ -370,7 +397,7 @@ bool SSAPH::OptimizeAddress(MachineInstr *MI, unsigned OpNo) {
       }
       break;
 
-    case X86::SHLir32:
+    case X86::SHLri32:
       // If this shift could be folded into the index portion of the address if
       // it were the index register, move it to the index register operand now,
       // so it will be folded in below.
@@ -388,7 +415,7 @@ bool SSAPH::OptimizeAddress(MachineInstr *MI, unsigned OpNo) {
   // Attempt to fold instructions used by the index into the instruction
   if (MachineInstr *DefInst = getDefiningInst(IndexRegOp)) {
     switch (DefInst->getOpcode()) {
-    case X86::SHLir32: {
+    case X86::SHLri32: {
       // Figure out what the resulting scale would be if we folded this shift.
       unsigned ResScale = Scale * (1 << DefInst->getOperand(2).getImmedValue());
       if (isValidScaleAmount(ResScale)) {
@@ -435,15 +462,15 @@ bool SSAPH::PeepholeOptimize(MachineBasicBlock &MBB,
   switch (MI->getOpcode()) {
 
     // Register to memory stores.  Format: <base,scale,indexreg,immdisp>, srcreg
-  case X86::MOVrm32: case X86::MOVrm16: case X86::MOVrm8:
-  case X86::MOVim32: case X86::MOVim16: case X86::MOVim8:
+  case X86::MOVmr32: case X86::MOVmr16: case X86::MOVmr8:
+  case X86::MOVmi32: case X86::MOVmi16: case X86::MOVmi8:
     // Check to see if we can fold the source instruction into this one...
     if (MachineInstr *SrcInst = getDefiningInst(MI->getOperand(4))) {
       switch (SrcInst->getOpcode()) {
         // Fold the immediate value into the store, if possible.
-      case X86::MOVir8:  return Propagate(MI, 4, SrcInst, 1, X86::MOVim8);
-      case X86::MOVir16: return Propagate(MI, 4, SrcInst, 1, X86::MOVim16);
-      case X86::MOVir32: return Propagate(MI, 4, SrcInst, 1, X86::MOVim32);
+      case X86::MOVri8:  return Propagate(MI, 4, SrcInst, 1, X86::MOVmi8);
+      case X86::MOVri16: return Propagate(MI, 4, SrcInst, 1, X86::MOVmi16);
+      case X86::MOVri32: return Propagate(MI, 4, SrcInst, 1, X86::MOVmi32);
       default: break;
       }
     }
@@ -453,9 +480,9 @@ bool SSAPH::PeepholeOptimize(MachineBasicBlock &MBB,
       return true;
     break;
 
-  case X86::MOVmr32:
-  case X86::MOVmr16:
-  case X86::MOVmr8:
+  case X86::MOVrm32:
+  case X86::MOVrm16:
+  case X86::MOVrm8:
     // If we can optimize the addressing expression, do so now.
     if (OptimizeAddress(MI, 1))
       return true;