#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Target/MRegisterInfo.h"
#include "Support/Statistic.h"
+#include "Support/STLExtras.h"
+
using namespace llvm;
namespace {
bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &I) {
assert(I != MBB.end());
- MachineBasicBlock::iterator NextI = I; ++NextI;
+ MachineBasicBlock::iterator NextI = next(I);
MachineInstr *MI = I;
MachineInstr *Next = (NextI != MBB.end()) ? &*NextI : (MachineInstr*)0;
// immediate despite the fact that the operands are 16 or 32 bits. Because
// this can save three bytes of code size (and icache space), we want to
// shrink them if possible.
- case X86::IMULri16: case X86::IMULri32:
+ case X86::IMULrri16: case X86::IMULrri32:
assert(MI->getNumOperands() == 3 && "These should all have 3 operands!");
if (MI->getOperand(2).isImmediate()) {
int Val = MI->getOperand(2).getImmedValue();
unsigned Opcode;
switch (MI->getOpcode()) {
default: assert(0 && "Unknown opcode value!");
- case X86::IMULri16: Opcode = X86::IMULri16b; break;
- case X86::IMULri32: Opcode = X86::IMULri32b; break;
+ case X86::IMULrri16: Opcode = X86::IMULrri16b; break;
+ case X86::IMULrri32: Opcode = X86::IMULrri32b; break;
}
unsigned R0 = MI->getOperand(0).getReg();
unsigned R1 = MI->getOperand(1).getReg();
}
return false;
+#if 0
+ case X86::IMULrmi16: case X86::IMULrmi32:
+ assert(MI->getNumOperands() == 6 && "These should all have 6 operands!");
+ if (MI->getOperand(5).isImmediate()) {
+ int Val = MI->getOperand(5).getImmedValue();
+ // If the value is the same when signed extended from 8 bits...
+ if (Val == (signed int)(signed char)Val) {
+ unsigned Opcode;
+ switch (MI->getOpcode()) {
+ default: assert(0 && "Unknown opcode value!");
+ case X86::IMULrmi16: Opcode = X86::IMULrmi16b; break;
+ case X86::IMULrmi32: Opcode = X86::IMULrmi32b; break;
+ }
+ unsigned R0 = MI->getOperand(0).getReg();
+ unsigned R1 = MI->getOperand(1).getReg();
+ unsigned Scale = MI->getOperand(2).getImmedValue();
+ unsigned R2 = MI->getOperand(3).getReg();
+ unsigned Offset = MI->getOperand(4).getImmedValue();
+ I = MBB.insert(MBB.erase(I),
+ BuildMI(Opcode, 5, R0).addReg(R1).addZImm(Scale).
+ addReg(R2).addSImm(Offset).addZImm((char)Val));
+ return true;
+ }
+ }
+ return false;
+#endif
+
case X86::ADDri16: case X86::ADDri32:
+ case X86::ADDmi16: case X86::ADDmi32:
case X86::SUBri16: case X86::SUBri32:
case X86::ANDri16: case X86::ANDri32:
case X86::ORri16: case X86::ORri32:
default: assert(0 && "Unknown opcode value!");
case X86::ADDri16: Opcode = X86::ADDri16b; break;
case X86::ADDri32: Opcode = X86::ADDri32b; break;
+ case X86::ADDmi16: Opcode = X86::ADDmi16b; break;
+ case X86::ADDmi32: Opcode = X86::ADDmi32b; break;
case X86::SUBri16: Opcode = X86::SUBri16b; break;
case X86::SUBri32: Opcode = X86::SUBri32b; break;
case X86::ANDri16: Opcode = X86::ANDri16b; break;
}
return false;
+
+ case X86::ANDmi16: case X86::ANDmi32:
+ assert(MI->getNumOperands() == 5 && "These should all have 5 operands!");
+ if (MI->getOperand(4).isImmediate()) {
+ int Val = MI->getOperand(4).getImmedValue();
+ // If the value is the same when signed extended from 8 bits...
+ if (Val == (signed int)(signed char)Val) {
+ unsigned Opcode;
+ switch (MI->getOpcode()) {
+ default: assert(0 && "Unknown opcode value!");
+ case X86::ANDmi16: Opcode = X86::ANDmi16b; break;
+ case X86::ANDmi32: Opcode = X86::ANDmi32b; break;
+ }
+ unsigned R0 = MI->getOperand(0).getReg();
+ unsigned Scale = MI->getOperand(1).getImmedValue();
+ unsigned R1 = MI->getOperand(2).getReg();
+ unsigned Offset = MI->getOperand(3).getImmedValue();
+ I = MBB.insert(MBB.erase(I),
+ BuildMI(Opcode, 5).addReg(R0).addZImm(Scale).
+ addReg(R1).addSImm(Offset).addZImm((char)Val));
+ return true;
+ }
+ }
+ return false;
+
#if 0
- case X86::MOVir32: Size++;
- case X86::MOVir16: Size++;
- case X86::MOVir8:
+ case X86::MOVri32: Size++;
+ case X86::MOVri16: Size++;
+ case X86::MOVri8:
// FIXME: We can only do this transformation if we know that flags are not
// used here, because XOR clobbers the flags!
if (MI->getOperand(1).isImmediate()) { // avoid mov EAX, <value>
// getDefinition - Return the machine instruction that defines the specified
// SSA virtual register.
MachineInstr *getDefinition(unsigned Reg) {
- assert(Reg >= MRegisterInfo::FirstVirtualRegister &&
+ assert(MRegisterInfo::isVirtualRegister(Reg) &&
"use-def chains only exist for SSA registers!");
assert(Reg - MRegisterInfo::FirstVirtualRegister < DefiningInst.size() &&
"Unknown register number!");
// Attempt to fold instructions used by the base register into the instruction
if (MachineInstr *DefInst = getDefiningInst(BaseRegOp)) {
switch (DefInst->getOpcode()) {
- case X86::MOVir32:
+ case X86::MOVri32:
// If there is no displacement set for this instruction set one now.
// FIXME: If we can fold two immediates together, we should do so!
if (DisplacementOp.isImmediate() && !DisplacementOp.getImmedValue()) {
}
break;
- case X86::SHLir32:
+ case X86::SHLri32:
// If this shift could be folded into the index portion of the address if
// it were the index register, move it to the index register operand now,
// so it will be folded in below.
// Attempt to fold instructions used by the index into the instruction
if (MachineInstr *DefInst = getDefiningInst(IndexRegOp)) {
switch (DefInst->getOpcode()) {
- case X86::SHLir32: {
+ case X86::SHLri32: {
// Figure out what the resulting scale would be if we folded this shift.
unsigned ResScale = Scale * (1 << DefInst->getOperand(2).getImmedValue());
if (isValidScaleAmount(ResScale)) {
bool SSAPH::PeepholeOptimize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &I) {
- MachineBasicBlock::iterator NextI = I; ++NextI;
+ MachineBasicBlock::iterator NextI = next(I);
MachineInstr *MI = I;
MachineInstr *Next = (NextI != MBB.end()) ? &*NextI : (MachineInstr*)0;
switch (MI->getOpcode()) {
// Register to memory stores. Format: <base,scale,indexreg,immdisp>, srcreg
- case X86::MOVrm32: case X86::MOVrm16: case X86::MOVrm8:
- case X86::MOVim32: case X86::MOVim16: case X86::MOVim8:
+ case X86::MOVmr32: case X86::MOVmr16: case X86::MOVmr8:
+ case X86::MOVmi32: case X86::MOVmi16: case X86::MOVmi8:
// Check to see if we can fold the source instruction into this one...
if (MachineInstr *SrcInst = getDefiningInst(MI->getOperand(4))) {
switch (SrcInst->getOpcode()) {
// Fold the immediate value into the store, if possible.
- case X86::MOVir8: return Propagate(MI, 4, SrcInst, 1, X86::MOVim8);
- case X86::MOVir16: return Propagate(MI, 4, SrcInst, 1, X86::MOVim16);
- case X86::MOVir32: return Propagate(MI, 4, SrcInst, 1, X86::MOVim32);
+ case X86::MOVri8: return Propagate(MI, 4, SrcInst, 1, X86::MOVmi8);
+ case X86::MOVri16: return Propagate(MI, 4, SrcInst, 1, X86::MOVmi16);
+ case X86::MOVri32: return Propagate(MI, 4, SrcInst, 1, X86::MOVmi32);
default: break;
}
}
return true;
break;
- case X86::MOVmr32:
- case X86::MOVmr16:
- case X86::MOVmr8:
+ case X86::MOVrm32:
+ case X86::MOVrm16:
+ case X86::MOVrm8:
// If we can optimize the addressing expression, do so now.
if (OptimizeAddress(MI, 1))
return true;
projects / oota-llvm.git / blobdiff