-no-implicit-float means explicit fp operations are legal.

[oota-llvm.git] / lib / Target / X86 / X86RegisterInfo.cpp

diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 0130ba2c49dfef09e86e2bfe0c44c899813d00cf..310290213f72084971d4a364ea61ab874a7c4801 100644 (file)
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -332,7 +332,7 @@ bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
 }
 
 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
-  const MachineFrameInfo *MFI = MF.getFrameInfo();;
+  const MachineFrameInfo *MFI = MF.getFrameInfo();
 
   // FIXME: Currently we don't support stack realignment for functions with
   // variable-sized allocas
@@ -542,11 +542,14 @@ void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
        (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
        (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
   uint64_t Chunk = (1LL << 31) - 1;
+  DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
+                 DebugLoc::getUnknownLoc());
 
   while (Offset) {
     uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
     MachineInstr *MI =
-      BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
+      BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
+         .addReg(StackPtr).addImm(ThisVal);
     // The EFLAGS implicit def is dead.
     MI->getOperand(3).setIsDead();
     Offset -= ThisVal;
@@ -726,12 +729,15 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
   bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
                           !Fn->doesNotThrow() ||
                           UnwindTablesMandatory;
-  DebugLoc DL = DebugLoc::getUnknownLoc();
+  DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
+                 DebugLoc::getUnknownLoc());
+
   // Prepare for frame info.
   unsigned FrameLabelId = 0;
 
   // Get the number of bytes to allocate from the FrameInfo.
   uint64_t StackSize = MFI->getStackSize();
+
   // Get desired stack alignment
   uint64_t MaxAlign  = MFI->getMaxAlignment();
 
@@ -810,8 +816,9 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
       // The EFLAGS implicit def is dead.
       MI->getOperand(3).setIsDead();
     }
-  } else
+  } else {
     NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
+  }
 
   unsigned ReadyLabelId = 0;
   if (needsFrameMoves) {
@@ -826,6 +833,9 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
           MBBI->getOpcode() == X86::PUSH64r))
     ++MBBI;
 
+  if (MBBI != MBB.end())
+    DL = MBBI->getDebugLoc();
+
   if (NumBytes) {   // adjust stack pointer: ESP -= numbytes
     if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
       // Check, whether EAX is livein for this function
@@ -843,7 +853,8 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
       // necessary to ensure that the guard pages used by the OS virtual memory
       // manager are allocated in correct sequence.
       if (!isEAXAlive) {
-        BuildMI(MBB, MBBI,DL, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
+        BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
+          .addImm(NumBytes);
         BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
           .addExternalSymbol("_alloca");
       } else {
@@ -886,7 +897,7 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
   X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
   MachineBasicBlock::iterator MBBI = prior(MBB.end());
   unsigned RetOpcode = MBBI->getOpcode();
-  DebugLoc DL = DebugLoc::getUnknownLoc();
+  DebugLoc DL = MBBI->getDebugLoc();
 
   switch (RetOpcode) {
   case X86::RET:
@@ -919,10 +930,11 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
     NumBytes = FrameSize - CSSize;
 
     // pop EBP.
-    BuildMI(MBB, MBBI, DL, 
+    BuildMI(MBB, MBBI, DL,
             TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
-  } else
+  } else {
     NumBytes = StackSize - CSSize;
+  }
 
   // Skip the callee-saved pop instructions.
   MachineBasicBlock::iterator LastCSPop = MBBI;
@@ -935,6 +947,8 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
     --MBBI;
   }
 
+  DL = MBBI->getDebugLoc();
+
   // If there is an ADD32ri or SUB32ri of ESP immediately before this
   // instruction, merge the two instructions.
   if (NumBytes || MFI->hasVarSizedObjects())
@@ -994,19 +1008,22 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
     // Incoporate the retaddr area.
     Offset = StackAdj-MaxTCDelta;
     assert(Offset >= 0 && "Offset should never be negative");
+
     if (Offset) {
       // Check for possible merge with preceeding ADD instruction.
       Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
       emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
     }
+
     // Jump to label or value in register.
     if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
       BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPd)).
         addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
-    else if (RetOpcode== X86::TCRETURNri64) {
+    else if (RetOpcode== X86::TCRETURNri64)
       BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
-    } else
+    else
        BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg());
+
     // Delete the pseudo instruction TCRETURN.
     MBB.erase(MBBI);
   } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&