#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineLocation.h"
#include "llvm/Target/TargetFrameInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Support/CommandLine.h"
+#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
-#include <iostream>
-
using namespace llvm;
namespace {
Opc = X86::MOVSDmr;
} else if (RC == &X86::VR128RegClass) {
Opc = X86::MOVAPSmr;
+ } else if (RC == &X86::VR64RegClass) {
+ Opc = X86::MMX_MOVQ64mr;
} else {
assert(0 && "Unknown regclass");
abort();
}
- addFrameReference(BuildMI(MBB, MI, TII.get(Opc)), FrameIdx).addReg(SrcReg);
+ addFrameReference(BuildMI(MBB, MI, TII.get(Opc)), FrameIdx)
+ .addReg(SrcReg, false, false, true);
}
void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Opc = X86::MOVSDrm;
} else if (RC == &X86::VR128RegClass) {
Opc = X86::MOVAPSrm;
+ } else if (RC == &X86::VR64RegClass) {
+ Opc = X86::MMX_MOVQ64rm;
} else {
assert(0 && "Unknown regclass");
abort();
Opc = X86::FsMOVAPDrr;
} else if (RC == &X86::VR128RegClass) {
Opc = X86::MOVAPSrr;
+ } else if (RC == &X86::VR64RegClass) {
+ Opc = X86::MMX_MOVQ64rr;
} else {
assert(0 && "Unknown regclass");
abort();
BuildMI(MBB, MI, TII.get(Opc), DestReg).addReg(SrcReg);
}
+
+void X86RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I,
+ unsigned DestReg,
+ const MachineInstr *Orig) const {
+ MachineInstr *MI = Orig->clone();
+ MI->getOperand(0).setReg(DestReg);
+ MBB.insert(I, MI);
+}
+
static MachineInstr *FuseTwoAddrInst(unsigned Opcode, unsigned FrameIndex,
MachineInstr *MI,
const TargetInstrInfo &TII) {
MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
else if (MO.isJumpTableIndex())
MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex());
+ else if (MO.isExternalSymbol())
+ MIB = MIB.addExternalSymbol(MO.getSymbolName());
else
assert(0 && "Unknown operand type!");
}
MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
else if (MO.isJumpTableIndex())
MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex());
+ else if (MO.isExternalSymbol())
+ MIB = MIB.addExternalSymbol(MO.getSymbolName());
else
assert(0 && "Unknown operand for FuseInst!");
}
static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
for (unsigned i = 1; i != NumEntries; ++i)
if (!(Table[i-1] < Table[i])) {
- std::cerr << "Entries out of order " << Table[i-1].from
- << " " << Table[i].from << "\n";
+ cerr << "Entries out of order " << Table[i-1].from
+ << " " << Table[i].from << "\n";
return false;
}
return true;
bool isTwoAddrFold = false;
unsigned NumOps = TII.getNumOperands(MI->getOpcode());
bool isTwoAddr = NumOps > 1 &&
- TII.getOperandConstraint(MI->getOpcode(), 1,TargetInstrInfo::TIED_TO) != -1;
+ MI->getInstrDescriptor()->getOperandConstraint(1, TOI::TIED_TO) != -1;
MachineInstr *NewMI = NULL;
// Folding a memory location into the two-address part of a two-address
{ X86::MOVPQIto64rr,X86::MOVPQIto64mr },
{ X86::MOVPS2SSrr, X86::MOVPS2SSmr },
{ X86::MOVSDrr, X86::MOVSDmr },
+ { X86::MOVSDto64rr, X86::MOVSDto64mr },
+ { X86::MOVSS2DIrr, X86::MOVSS2DImr },
{ X86::MOVSSrr, X86::MOVSSmr },
{ X86::MOVUPDrr, X86::MOVUPDmr },
{ X86::MOVUPSrr, X86::MOVUPSmr },
{ X86::MOV32rr, X86::MOV32rm },
{ X86::MOV64rr, X86::MOV64rm },
{ X86::MOV64toPQIrr, X86::MOV64toPQIrm },
+ { X86::MOV64toSDrr, X86::MOV64toSDrm },
{ X86::MOV8rr, X86::MOV8rm },
{ X86::MOVAPDrr, X86::MOVAPDrm },
{ X86::MOVAPSrr, X86::MOVAPSrm },
{ X86::MOVDDUPrr, X86::MOVDDUPrm },
{ X86::MOVDI2PDIrr, X86::MOVDI2PDIrm },
+ { X86::MOVDI2SSrr, X86::MOVDI2SSrm },
{ X86::MOVSD2PDrr, X86::MOVSD2PDrm },
{ X86::MOVSDrr, X86::MOVSDrm },
{ X86::MOVSHDUPrr, X86::MOVSHDUPrm },
// No fusion
if (PrintFailedFusing)
- std::cerr << "We failed to fuse ("
- << ((i == 1) ? "r" : "s") << "): " << *MI;
+ cerr << "We failed to fuse ("
+ << ((i == 1) ? "r" : "s") << "): " << *MI;
return NULL;
}
-const unsigned *X86RegisterInfo::getCalleeSaveRegs() const {
- static const unsigned CalleeSaveRegs32Bit[] = {
+const unsigned *X86RegisterInfo::getCalleeSavedRegs() const {
+ static const unsigned CalleeSavedRegs32Bit[] = {
X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
};
- static const unsigned CalleeSaveRegs64Bit[] = {
+ static const unsigned CalleeSavedRegs64Bit[] = {
X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
};
- return Is64Bit ? CalleeSaveRegs64Bit : CalleeSaveRegs32Bit;
+ return Is64Bit ? CalleeSavedRegs64Bit : CalleeSavedRegs32Bit;
}
const TargetRegisterClass* const*
-X86RegisterInfo::getCalleeSaveRegClasses() const {
- static const TargetRegisterClass * const CalleeSaveRegClasses32Bit[] = {
+X86RegisterInfo::getCalleeSavedRegClasses() const {
+ static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
&X86::GR32RegClass, &X86::GR32RegClass,
&X86::GR32RegClass, &X86::GR32RegClass, 0
};
- static const TargetRegisterClass * const CalleeSaveRegClasses64Bit[] = {
+ static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
&X86::GR64RegClass, &X86::GR64RegClass,
&X86::GR64RegClass, &X86::GR64RegClass,
&X86::GR64RegClass, &X86::GR64RegClass, 0
};
- return Is64Bit ? CalleeSaveRegClasses64Bit : CalleeSaveRegClasses32Bit;
+ return Is64Bit ? CalleeSavedRegClasses64Bit : CalleeSavedRegClasses32Bit;
+}
+
+BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
+ BitVector Reserved(getNumRegs());
+ Reserved.set(X86::RSP);
+ Reserved.set(X86::ESP);
+ Reserved.set(X86::SP);
+ Reserved.set(X86::SPL);
+ if (hasFP(MF)) {
+ Reserved.set(X86::RBP);
+ Reserved.set(X86::EBP);
+ Reserved.set(X86::BP);
+ Reserved.set(X86::BPL);
+ }
+ return Reserved;
}
//===----------------------------------------------------------------------===//
// pointer register. This is true if the function has variable sized allocas or
// if frame pointer elimination is disabled.
//
-static bool hasFP(const MachineFunction &MF) {
+bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
return (NoFramePointerElim ||
MF.getFrameInfo()->hasVarSizedObjects() ||
MF.getInfo<X86FunctionInfo>()->getForceFramePointer());
unsigned Opc = (Amount < 128) ?
(Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
(Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
- New = BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount);
+ New = BuildMI(TII.get(Opc), StackPtr)
+ .addReg(StackPtr).addImm(Amount);
}
}
MBB.erase(I);
}
-void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
+void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
+ RegScavenger *RS) const{
unsigned i = 0;
MachineInstr &MI = *II;
MachineFunction &MF = *MI.getParent()->getParent();
const Function* Fn = MF.getFunction();
const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
MachineInstr *MI;
+ MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
+
+ // Prepare for frame info.
+ unsigned FrameLabelId = 0;
// Get the number of bytes to allocate from the FrameInfo
unsigned NumBytes = MFI->getStackSize();
- if (MFI->hasCalls() || MF.getFrameInfo()->hasVarSizedObjects()) {
- // When we have no frame pointer, we reserve argument space for call sites
- // in the function immediately on entry to the current function. This
- // eliminates the need for add/sub ESP brackets around call sites.
- //
- if (!hasFP(MF))
- NumBytes += MFI->getMaxCallFrameSize();
-
- // Round the size to a multiple of the alignment (don't forget the 4/8 byte
- // offset though).
- NumBytes = ((NumBytes+SlotSize)+Align-1)/Align*Align - SlotSize;
- }
-
- // Update frame info to pretend that this is part of the stack...
- MFI->setStackSize(NumBytes);
if (NumBytes) { // adjust stack pointer: ESP -= numbytes
- if (NumBytes >= 4096 && Subtarget->isTargetCygwin()) {
+ if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
// Function prologue calls _alloca to probe the stack when allocating
// more than 4k bytes in one go. Touching the stack at 4K increments is
// necessary to ensure that the guard pages used by the OS virtual memory
}
}
+ if (MMI && MMI->needsFrameInfo()) {
+ // Mark effective beginning of when frame pointer becomes valid.
+ FrameLabelId = MMI->NextLabelID();
+ BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId);
+ }
+
if (hasFP(MF)) {
// Get the offset of the stack slot for the EBP register... which is
// guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
MBB.insert(MBBI, MI);
}
+ if (MMI && MMI->needsFrameInfo()) {
+ std::vector<MachineMove> &Moves = MMI->getFrameMoves();
+
+ if (NumBytes) {
+ // Show update of SP.
+ MachineLocation SPDst(MachineLocation::VirtualFP);
+ MachineLocation SPSrc(MachineLocation::VirtualFP, -NumBytes);
+ Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
+ } else {
+ MachineLocation SP(StackPtr);
+ Moves.push_back(MachineMove(FrameLabelId, SP, SP));
+ }
+
+ // Add callee saved registers to move list.
+ const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
+ for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
+ int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
+ unsigned Reg = CSI[I].getReg();
+ MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
+ MachineLocation CSSrc(Reg);
+ Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
+ }
+
+ // Mark effective beginning of when frame pointer is ready.
+ unsigned ReadyLabelId = MMI->NextLabelID();
+ BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId);
+
+ MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
+ MachineLocation FPSrc(MachineLocation::VirtualFP);
+ Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
+ }
+
// If it's main() on Cygwin\Mingw32 we should align stack as well
if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
- Subtarget->isTargetCygwin()) {
- MI= BuildMI(TII.get(X86::AND32ri), X86::ESP).addReg(X86::ESP).addImm(-Align);
+ Subtarget->isTargetCygMing()) {
+ MI= BuildMI(TII.get(X86::AND32ri), X86::ESP)
+ .addReg(X86::ESP).addImm(-Align);
MBB.insert(MBBI, MI);
// Probe the stack
unsigned Opc = (NumBytes < 128) ?
(Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
(Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
- BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(NumBytes);
+ BuildMI(MBB, MBBI, TII.get(Opc), StackPtr)
+ .addReg(StackPtr).addImm(NumBytes);
} else if ((int)NumBytes < 0) {
unsigned Opc = (-NumBytes < 128) ?
(Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
- BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(-NumBytes);
+ BuildMI(MBB, MBBI, TII.get(Opc), StackPtr)
+ .addReg(StackPtr).addImm(-NumBytes);
}
}
}
return hasFP(MF) ? FramePtr : StackPtr;
}
+void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
+ const {
+ // Initial state of the frame pointer is esp.
+ MachineLocation Dst(MachineLocation::VirtualFP);
+ MachineLocation Src(StackPtr, 0);
+ Moves.push_back(MachineMove(0, Dst, Src));
+}
+
+unsigned X86RegisterInfo::getEHExceptionRegister() const {
+ assert(0 && "What is the exception register");
+ return 0;
+}
+
+unsigned X86RegisterInfo::getEHHandlerRegister() const {
+ assert(0 && "What is the exception handler register");
+ return 0;
+}
+
namespace llvm {
unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
switch (VT) {
projects / oota-llvm.git / blobdiff