Implement folding of loads into floating point operations. This implements:

[oota-llvm.git] / lib / Target / X86 / X86RegisterInfo.td

diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td
index ee491ee6ff53d92d7d1d831b96f8ce377cec8407..497f343294eebde4e7ce8f77f774401a2a02070c 100644 (file)
--- a/lib/Target/X86/X86RegisterInfo.td
+++ b/lib/Target/X86/X86RegisterInfo.td
@@ -1,4 +1,11 @@
 //===- X86RegisterInfo.td - Describe the X86 Register File ------*- C++ -*-===//
+// 
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// 
+//===----------------------------------------------------------------------===//
 //
 // This file describes the X86 Register file, defining the registers themselves,
 // aliases between the registers, and the register classes built out of the
@@ -9,7 +16,7 @@
 //===----------------------------------------------------------------------===//
 //  Register definitions...
 //
-set Namespace = "X86" in {
+let Namespace = "X86" in {
   // 32-bit registers
   def EAX : Register; def ECX : Register;
   def EDX : Register; def EBX : Register;
@@ -35,17 +42,17 @@ set Namespace = "X86" in {
   def FP6 : Register; 
 
   // Floating point stack registers
-  def ST0 : Register; def ST1 : Register;
-  def ST2 : Register; def ST3 : Register;
-  def ST4 : Register; def ST5 : Register;
-  def ST6 : Register; def ST7 : Register; 
+  def ST0 : NamedReg<"ST(0)">; def ST1 : NamedReg<"ST(1)">;
+  def ST2 : NamedReg<"ST(2)">; def ST3 : NamedReg<"ST(3)">;
+  def ST4 : NamedReg<"ST(4)">; def ST5 : NamedReg<"ST(5)">;
+  def ST6 : NamedReg<"ST(6)">; def ST7 : NamedReg<"ST(7)">; 
   
   // Flags, Segment registers, etc...
   
   // This is a slimy hack to make it possible to say that flags are clobbered...
   // Ideally we'd model instructions based on which particular flag(s) they
   // could clobber. 
-  def EFLAGS : Register;
+  //def EFLAGS : Register;
 }
 
 //===----------------------------------------------------------------------===//
@@ -69,20 +76,20 @@ def : RegisterAliases<SP, [ESP]>;     def : RegisterAliases<BP, [EBP]>;
 // top-level register classes.  The order specified in the register list is
 // implicitly defined to be the register allocation order.
 //
-def r8  : RegisterClass<i8,  1, [AL, CL, DL, BL, AH, CH, DH, BH]>;
-def r16 : RegisterClass<i16, 2, [AX, CX, DX, BX, SI, DI, BP, SP]> {
-  set Methods = [{
+def R8  : RegisterClass<i8,  1, [AL, AH, CL, CH, DL, DH, BL, BH]>;
+def R16 : RegisterClass<i16, 2, [AX, CX, DX, SI, DI, BX, BP, SP]> {
+  let Methods = [{
     iterator allocation_order_end(MachineFunction &MF) const {
       if (hasFP(MF))     // Does the function dedicate EBP to being a frame ptr?
-       return end()-2;  // If so, don't allocate SP or BP
+        return end()-2;  // If so, don't allocate SP or BP
       else
-       return end()-1;  // If not, just don't allocate SP
+        return end()-1;  // If not, just don't allocate SP
     }
   }];
 }
 
-def r32 : RegisterClass<i32, 4, [EAX, ECX, EDX, EBX, ESI, EDI, EBP, ESP]> {
-  set Methods = [{
+def R32 : RegisterClass<i32, 4, [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
+  let Methods = [{
     iterator allocation_order_end(MachineFunction &MF) const {
       if (hasFP(MF))     // Does the function dedicate EBP to being a frame ptr?
         return end()-2;  // If so, don't allocate ESP or EBP
@@ -92,9 +99,9 @@ def r32 : RegisterClass<i32, 4, [EAX, ECX, EDX, EBX, ESI, EDI, EBP, ESP]> {
   }];
 }
 
-def rFP : RegisterClass<f80, 4, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
+def RFP : RegisterClass<f80, 4, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
 
 // Registers which cannot be allocated... and are thus left unnamed.
 def : RegisterClass<f80, 4, [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]>;
-def : RegisterClass<i16, 2, [EFLAGS]>;
+//def : RegisterClass<i16, 2, [EFLAGS]>;