Since I'm obliged to work with a development OS that currently doesn't

[oota-llvm.git] / lib / Target / X86 / X86RegisterInfo.td

diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td
index eacfda7e5b254e56c70b25b1ec7fe1ea00be338f..7303e8a40d4e9d0c0ad0488d047f2e57d436a8e5 100644 (file)
--- a/lib/Target/X86/X86RegisterInfo.td
+++ b/lib/Target/X86/X86RegisterInfo.td
@@ -226,29 +226,34 @@ def : SubRegSet<3, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
 // R8B, ... R15B. 
+// Allocate R12 and R13 last, as these require an extra byte when
+// encoded in x86_64 instructions.
 // FIXME: Allow AH, CH, DH, BH in 64-mode for non-REX instructions,
 def GR8 : RegisterClass<"X86", [i8],  8,
                         [AL, CL, DL, BL, AH, CH, DH, BH, SIL, DIL, BPL, SPL,
-                         R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]> {
+                         R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B]> {
   let MethodProtos = [{
     iterator allocation_order_begin(const MachineFunction &MF) const;
     iterator allocation_order_end(const MachineFunction &MF) const;
   }];
   let MethodBodies = [{
-      // Does the function dedicate RBP / EBP to being a frame ptr?
-      // If so, don't allocate SPL or BPL.
-      static const unsigned X86_GR8_AO_64_fp[] =
-      {X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
-       X86::R8B, X86::R9B, X86::R10B, X86::R11B,
-       X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B};
-      // If not, just don't allocate SPL.
-      static const unsigned X86_GR8_AO_64[] =
-      {X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
-       X86::R8B, X86::R9B, X86::R10B, X86::R11B,
-       X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::BPL};
-      // In 32-mode, none of the 8-bit registers aliases EBP or ESP.
-      static const unsigned X86_GR8_AO_32[] =
-      {X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH};
+    // Does the function dedicate RBP / EBP to being a frame ptr?
+    // If so, don't allocate SPL or BPL.
+    static const unsigned X86_GR8_AO_64_fp[] = {
+      X86::AL,   X86::CL,   X86::DL,   X86::SIL, X86::DIL,
+      X86::R8B,  X86::R9B,  X86::R10B, X86::R11B,
+      X86::BL,   X86::R14B, X86::R15B, X86::R12B, X86::R13B
+    };
+    // If not, just don't allocate SPL.
+    static const unsigned X86_GR8_AO_64[] = {
+      X86::AL,   X86::CL,   X86::DL,   X86::SIL, X86::DIL,
+      X86::R8B,  X86::R9B,  X86::R10B, X86::R11B,
+      X86::BL,   X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::BPL
+    };
+    // In 32-mode, none of the 8-bit registers aliases EBP or ESP.
+    static const unsigned X86_GR8_AO_32[] = {
+      X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH
+    };
 
     GR8Class::iterator
     GR8Class::allocation_order_begin(const MachineFunction &MF) const {
@@ -281,28 +286,32 @@ def GR8 : RegisterClass<"X86", [i8],  8,
 
 def GR16 : RegisterClass<"X86", [i16], 16,
                          [AX, CX, DX, SI, DI, BX, BP, SP,
-                          R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]> {
+                          R8W, R9W, R10W, R11W, R14W, R15W, R12W, R13W]> {
   let SubRegClassList = [GR8];
   let MethodProtos = [{
     iterator allocation_order_begin(const MachineFunction &MF) const;
     iterator allocation_order_end(const MachineFunction &MF) const;
   }];
   let MethodBodies = [{
-      // Does the function dedicate RBP / EBP to being a frame ptr?
-      // If so, don't allocate SP or BP.
-      static const unsigned X86_GR16_AO_64_fp[] =
-      {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
-       X86::R8W, X86::R9W, X86::R10W, X86::R11W,
-       X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W};
-      static const unsigned X86_GR16_AO_32_fp[] =
-      {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX};
-      // If not, just don't allocate SPL.
-      static const unsigned X86_GR16_AO_64[] =
-      {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
-       X86::R8W, X86::R9W, X86::R10W, X86::R11W,
-       X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::BP};
-      static const unsigned X86_GR16_AO_32[] =
-      {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP};
+    // Does the function dedicate RBP / EBP to being a frame ptr?
+    // If so, don't allocate SP or BP.
+    static const unsigned X86_GR16_AO_64_fp[] = {
+      X86::AX,  X86::CX,   X86::DX,   X86::SI,   X86::DI,
+      X86::R8W, X86::R9W,  X86::R10W, X86::R11W,
+      X86::BX, X86::R14W, X86::R15W,  X86::R12W, X86::R13W
+    };
+    static const unsigned X86_GR16_AO_32_fp[] = {
+      X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX
+    };
+    // If not, just don't allocate SPL.
+    static const unsigned X86_GR16_AO_64[] = {
+      X86::AX,  X86::CX,   X86::DX,   X86::SI,   X86::DI,
+      X86::R8W, X86::R9W,  X86::R10W, X86::R11W,
+      X86::BX, X86::R14W, X86::R15W,  X86::R12W, X86::R13W, X86::BP
+    };
+    static const unsigned X86_GR16_AO_32[] = {
+      X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP
+    };
 
     GR16Class::iterator
     GR16Class::allocation_order_begin(const MachineFunction &MF) const {
@@ -345,28 +354,32 @@ def GR16 : RegisterClass<"X86", [i16], 16,
 
 def GR32 : RegisterClass<"X86", [i32], 32, 
                          [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
-                          R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]> {
+                          R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D]> {
   let SubRegClassList = [GR8, GR16];
   let MethodProtos = [{
     iterator allocation_order_begin(const MachineFunction &MF) const;
     iterator allocation_order_end(const MachineFunction &MF) const;
   }];
   let MethodBodies = [{
-      // Does the function dedicate RBP / EBP to being a frame ptr?
-      // If so, don't allocate ESP or EBP.
-      static const unsigned X86_GR32_AO_64_fp[] =
-      {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
-       X86::R8D, X86::R9D, X86::R10D, X86::R11D,
-       X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D};
-      static const unsigned X86_GR32_AO_32_fp[] =
-      {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX};
-      // If not, just don't allocate SPL.
-      static const unsigned X86_GR32_AO_64[] =
-      {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
-       X86::R8D, X86::R9D, X86::R10D, X86::R11D,
-       X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP};
-      static const unsigned X86_GR32_AO_32[] =
-      {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP};
+    // Does the function dedicate RBP / EBP to being a frame ptr?
+    // If so, don't allocate ESP or EBP.
+    static const unsigned X86_GR32_AO_64_fp[] = {
+      X86::EAX, X86::ECX,  X86::EDX,  X86::ESI,  X86::EDI,
+      X86::R8D, X86::R9D,  X86::R10D, X86::R11D,
+      X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D
+    };
+    static const unsigned X86_GR32_AO_32_fp[] = {
+      X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX
+    };
+    // If not, just don't allocate SPL.
+    static const unsigned X86_GR32_AO_64[] = {
+      X86::EAX, X86::ECX,  X86::EDX,  X86::ESI,  X86::EDI,
+      X86::R8D, X86::R9D,  X86::R10D, X86::R11D,
+      X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP
+    };
+    static const unsigned X86_GR32_AO_32[] = {
+      X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP
+    };
 
     GR32Class::iterator
     GR32Class::allocation_order_begin(const MachineFunction &MF) const {
@@ -440,6 +453,9 @@ def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
   let SubRegClassList = [GR8, GR16];
 }
 
+// A class to support the 'A' assembler constraint: EAX then EDX.
+def GRAD : RegisterClass<"X86", [i32], 32, [EAX, EDX]>;
+
 // Scalar SSE2 floating point registers.
 def FR32 : RegisterClass<"X86", [f32], 32,
                          [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,