let LoadLatency = 4;
let MispredictPenalty = 16;
+ // Based on the LSD (loop-stream detector) queue size and benchmarking data.
+ let LoopMicroOpBufferSize = 50;
+
// FIXME: SSE4 and AVX are unimplemented. This flag is set to allow
// the scheduler to assign a default model to unrecognized opcodes.
let CompleteModel = 0;
def HWPort01 : ProcResGroup<[HWPort0, HWPort1]>;
def HWPort23 : ProcResGroup<[HWPort2, HWPort3]>;
def HWPort237 : ProcResGroup<[HWPort2, HWPort3, HWPort7]>;
+def HWPort04 : ProcResGroup<[HWPort0, HWPort4]>;
def HWPort05 : ProcResGroup<[HWPort0, HWPort5]>;
def HWPort06 : ProcResGroup<[HWPort0, HWPort6]>;
def HWPort15 : ProcResGroup<[HWPort1, HWPort5]>;
def HWPort16 : ProcResGroup<[HWPort1, HWPort6]>;
+def HWPort56: ProcResGroup<[HWPort5, HWPort6]>;
def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>;
def HWPort056: ProcResGroup<[HWPort0, HWPort5, HWPort6]>;
def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>;
def : WriteRes<WriteFence, [HWPort23, HWPort4]>;
def : WriteRes<WriteNop, []>;
-// Exceptions.
+//================ Exceptions ================//
//-- Specific Scheduling Models --//
-def Write2ALU : SchedWriteRes<[HWPort0156]> {
+def WriteP0 : SchedWriteRes<[HWPort0]>;
+def WriteP1 : SchedWriteRes<[HWPort1]>;
+def WriteP1_P23 : SchedWriteRes<[HWPort1, HWPort23]> {
+ let NumMicroOps = 2;
+}
+def WriteP1_Lat3 : SchedWriteRes<[HWPort1]> {
+ let Latency = 3;
+}
+def WriteP1_Lat3Ld : SchedWriteRes<[HWPort1, HWPort23]> {
+ let Latency = 7;
+}
+
+def Write2P0156_Lat2 : SchedWriteRes<[HWPort0156]> {
let Latency = 2;
let ResourceCycles = [2];
}
-def Write2ALULd : SchedWriteRes<[HWPort0156, HWPort23]> {
+def Write2P0156_Lat2Ld : SchedWriteRes<[HWPort0156, HWPort23]> {
let Latency = 6;
let ResourceCycles = [2, 1];
}
-def Write3ALU : SchedWriteRes<[HWPort0156]> {
- let Latency = 3;
- let ResourceCycles = [3];
+def Write5P0156 : SchedWriteRes<[HWPort0156]> {
+ let NumMicroOps = 5;
+ let ResourceCycles = [5];
}
-def WriteStore2Addr1Data : SchedWriteRes<[HWPort237, HWPort4]> {
+def Write2P237_P4 : SchedWriteRes<[HWPort237, HWPort4]> {
let Latency = 1;
let ResourceCycles = [2, 1];
}
-def WritePort06 : SchedWriteRes<[HWPort06]>;
+def WriteP01 : SchedWriteRes<[HWPort01]>;
-def WriteALUStore2Addr1Data : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
- let Latency = 1;
- let ResourceCycles = [1, 2, 1];
+def Write2P01 : SchedWriteRes<[HWPort01]> {
+ let NumMicroOps = 2;
}
-
-def Write2ALUStore2Addr1Data : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
- let Latency = 1;
- let ResourceCycles = [2, 2, 1];
+def Write3P01 : SchedWriteRes<[HWPort01]> {
+ let NumMicroOps = 3;
}
-def Write3ALUStore2Addr1Data : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
- let Latency = 1;
- let ResourceCycles = [3, 2, 1];
+def WriteP015 : SchedWriteRes<[HWPort015]>;
+
+def WriteP01_P5 : SchedWriteRes<[HWPort01, HWPort5]> {
+ let NumMicroOps = 2;
}
+def WriteP06 : SchedWriteRes<[HWPort06]>;
-def Write2Shift : SchedWriteRes<[HWPort06]> {
+def Write2P06 : SchedWriteRes<[HWPort06]> {
let Latency = 1;
let NumMicroOps = 2;
let ResourceCycles = [2];
}
-def Write3Shift : SchedWriteRes<[HWPort06]> {
- let Latency = 2;
- let NumMicroOps = 3;
- let ResourceCycles = [3];
-}
-
-def WriteP1Lat3 : SchedWriteRes<[HWPort1]> {
- let Latency = 3;
+def Write2P1 : SchedWriteRes<[HWPort1]> {
+ let NumMicroOps = 2;
+ let ResourceCycles = [2];
}
-def WriteP1Lat3Ld : SchedWriteRes<[HWPort1, HWPort23]> {
- let Latency = 7;
+def Write2P1_P23 : SchedWriteRes<[HWPort1, HWPort23]> {
+ let NumMicroOps = 3;
+ let ResourceCycles = [2, 1];
}
def WriteP15 : SchedWriteRes<[HWPort15]>;
def WriteP15Ld : SchedWriteRes<[HWPort15, HWPort23]> {
let Latency = 4;
}
-def WriteP01P5 : SchedWriteRes<[HWPort01, HWPort5]> {
- let NumMicroOps = 2;
+def Write3P06_Lat2 : SchedWriteRes<[HWPort06]> {
+ let Latency = 2;
+ let NumMicroOps = 3;
+ let ResourceCycles = [3];
}
def WriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
let NumMicroOps = 2;
}
-def Write2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
- let NumMicroOps = 3;
- let ResourceCycles = [2, 1];
-}
-def Write5P0156 : SchedWriteRes<[HWPort0156]> {
- let NumMicroOps = 5;
- let ResourceCycles = [5];
+def WriteP0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
+ let Latency = 1;
+ let ResourceCycles = [1, 2, 1];
}
-def WriteP01 : SchedWriteRes<[HWPort01]>;
-
-def Write2P01 : SchedWriteRes<[HWPort01]> {
- let NumMicroOps = 2;
+def Write2P0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
+ let Latency = 1;
+ let ResourceCycles = [2, 2, 1];
}
-def Write3P01 : SchedWriteRes<[HWPort01]> {
+def Write2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
let NumMicroOps = 3;
+ let ResourceCycles = [2, 1];
}
-def WriteP0 : SchedWriteRes<[HWPort0]>;
-def WriteP1 : SchedWriteRes<[HWPort1]>;
-def WriteP1_P23 : SchedWriteRes<[HWPort1, HWPort23]> {
- let NumMicroOps = 2;
+def Write3P0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
+ let Latency = 1;
+ let ResourceCycles = [3, 2, 1];
}
-def Write2P1 : SchedWriteRes<[HWPort1]> {
+def WriteP5 : SchedWriteRes<[HWPort5]>;
+def WriteP5Ld : SchedWriteRes<[HWPort5, HWPort23]> {
+ let Latency = 5;
let NumMicroOps = 2;
- let ResourceCycles = [2];
-}
-
-def Write2P1_P23 : SchedWriteRes<[HWPort1, HWPort23]> {
- let NumMicroOps = 3;
+ let ResourceCycles = [1, 1];
}
-def WriteP5 : SchedWriteRes<[HWPort5]>;
-
-def WriteP015 : SchedWriteRes<[HWPort015]>;
+// Notation:
+// - r: register.
+// - mm: 64 bit mmx register.
+// - x = 128 bit xmm register.
+// - (x)mm = mmx or xmm register.
+// - y = 256 bit ymm register.
+// - v = any vector register.
+// - m = memory.
//=== Integer Instructions ===//
//-- Move instructions --//
// MOV.
+// r16,m.
def : InstRW<[WriteALULd], (instregex "MOV16rm")>;
-// MOV with
+// MOVSX, MOVZX.
+// r,m.
def : InstRW<[WriteLoad], (instregex "MOV(S|Z)X32rm(8|16)")>;
// CMOVcc.
-def : InstRW<[Write2ALU],
+// r,r.
+def : InstRW<[Write2P0156_Lat2],
(instregex "CMOV(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)(16|32|64)rr")>;
-def : InstRW<[Write2ALULd, ReadAfterLd],
+// r,m.
+def : InstRW<[Write2P0156_Lat2Ld, ReadAfterLd],
(instregex "CMOV(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)(16|32|64)rm")>;
// XCHG.
+// r,r.
def WriteXCHG : SchedWriteRes<[HWPort0156]> {
let Latency = 2;
let ResourceCycles = [3];
def : InstRW<[WriteXCHG], (instregex "XCHG(8|16|32|64)rr", "XCHG(16|32|64)ar")>;
+// r,m.
def WriteXCHGrm : SchedWriteRes<[]> {
let Latency = 21;
let NumMicroOps = 8;
}
def : InstRW<[WriteXLAT], (instregex "XLAT")>;
-
// PUSH.
-def : InstRW<[WriteStore2Addr1Data], (instregex "PUSH(16|32)rmm")>;
+// m.
+def : InstRW<[Write2P237_P4], (instregex "PUSH(16|32)rmm")>;
+// PUSHF.
def WritePushF : SchedWriteRes<[HWPort1, HWPort4, HWPort237, HWPort06]> {
let NumMicroOps = 4;
}
def : InstRW<[WritePushF], (instregex "PUSHF(16|32)")>;
+// PUSHA.
def WritePushA : SchedWriteRes<[]> {
let NumMicroOps = 19;
}
def : InstRW<[WritePushA], (instregex "PUSHA(16|32)")>;
// POP.
-def : InstRW<[WriteStore2Addr1Data], (instregex "POP(16|32)rmm")>;
+// m.
+def : InstRW<[Write2P237_P4], (instregex "POP(16|32)rmm")>;
+// POPF.
def WritePopF : SchedWriteRes<[]> {
let NumMicroOps = 9;
}
def : InstRW<[WritePopF], (instregex "POPF(16|32)")>;
+// POPA.
def WritePopA : SchedWriteRes<[]> {
let NumMicroOps = 18;
}
def : InstRW<[WritePopA], (instregex "POPA(16|32)")>;
// LAHF SAHF.
-def : InstRW<[WritePort06], (instregex "(S|L)AHF")>;
+def : InstRW<[WriteP06], (instregex "(S|L)AHF")>;
// BSWAP.
+// r32.
def WriteBSwap32 : SchedWriteRes<[HWPort15]>;
def : InstRW<[WriteBSwap32], (instregex "BSWAP32r")>;
+// r64.
def WriteBSwap64 : SchedWriteRes<[HWPort06, HWPort15]> {
let NumMicroOps = 2;
}
def : InstRW<[WriteBSwap64], (instregex "BSWAP64r")>;
// MOVBE.
-def : InstRW<[Write2ALULd], (instregex "MOVBE(16|64)rm")>;
+// r16,m16 / r64,m64.
+def : InstRW<[Write2P0156_Lat2Ld], (instregex "MOVBE(16|64)rm")>;
+// r32, m32.
def WriteMoveBE32rm : SchedWriteRes<[HWPort15, HWPort23]> {
let NumMicroOps = 2;
}
def : InstRW<[WriteMoveBE32rm], (instregex "MOVBE32rm")>;
+// m16,r16.
def WriteMoveBE16mr : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
let NumMicroOps = 3;
}
def : InstRW<[WriteMoveBE16mr], (instregex "MOVBE16mr")>;
+// m32,r32.
def WriteMoveBE32mr : SchedWriteRes<[HWPort15, HWPort237, HWPort4]> {
let NumMicroOps = 3;
}
def : InstRW<[WriteMoveBE32mr], (instregex "MOVBE32mr")>;
+// m64,r64.
def WriteMoveBE64mr : SchedWriteRes<[HWPort06, HWPort15, HWPort237, HWPort4]> {
let NumMicroOps = 4;
}
def : InstRW<[WriteMoveBE64mr], (instregex "MOVBE64mr")>;
-
//-- Arithmetic instructions --//
+
// ADD SUB.
-def : InstRW<[Write2ALUStore2Addr1Data],
+// m,r/i.
+def : InstRW<[Write2P0156_2P237_P4],
(instregex "(ADD|SUB)(8|16|32|64)m(r|i)",
"(ADD|SUB)(8|16|32|64)mi8", "(ADD|SUB)64mi32")>;
// ADC SBB.
-def : InstRW<[Write2ALU], (instregex "(ADC|SBB)(8|16|32|64)r(r|i)",
+// r,r/i.
+def : InstRW<[Write2P0156_Lat2], (instregex "(ADC|SBB)(8|16|32|64)r(r|i)",
"(ADC|SBB)(16|32|64)ri8",
"(ADC|SBB)64ri32",
"(ADC|SBB)(8|16|32|64)rr_REV")>;
-def : InstRW<[Write2ALULd, ReadAfterLd], (instregex "(ADC|SBB)(8|16|32|64)rm")>;
+// r,m.
+def : InstRW<[Write2P0156_Lat2Ld, ReadAfterLd], (instregex "(ADC|SBB)(8|16|32|64)rm")>;
-def : InstRW<[Write3ALUStore2Addr1Data],
+// m,r/i.
+def : InstRW<[Write3P0156_2P237_P4],
(instregex "(ADC|SBB)(8|16|32|64)m(r|i)",
"(ADC|SBB)(16|32|64)mi8",
"(ADC|SBB)64mi32")>;
// INC DEC NOT NEG.
-def : InstRW<[WriteALUStore2Addr1Data],
+// m.
+def : InstRW<[WriteP0156_2P237_P4],
(instregex "(INC|DEC|NOT|NEG)(8|16|32|64)m",
"(INC|DEC)64(16|32)m")>;
-
+
// MUL IMUL.
+// r16.
def WriteMul16 : SchedWriteRes<[HWPort1, HWPort0156]> {
let Latency = 4;
let NumMicroOps = 4;
}
+def : InstRW<[WriteMul16], (instregex "IMUL16r", "MUL16r")>;
+
+// m16.
def WriteMul16Ld : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> {
let Latency = 8;
let NumMicroOps = 5;
}
-def : InstRW<[WriteMul16], (instregex "IMUL16r", "MUL16r")>;
def : InstRW<[WriteMul16Ld], (instregex "IMUL16m", "MUL16m")>;
+// r32.
def WriteMul32 : SchedWriteRes<[HWPort1, HWPort0156]> {
let Latency = 4;
let NumMicroOps = 3;
}
+def : InstRW<[WriteMul32], (instregex "IMUL32r", "MUL32r")>;
+
+// m32.
def WriteMul32Ld : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> {
let Latency = 8;
let NumMicroOps = 4;
}
-def : InstRW<[WriteMul32], (instregex "IMUL32r", "MUL32r")>;
def : InstRW<[WriteMul32Ld], (instregex "IMUL32m", "MUL32m")>;
+// r64.
def WriteMul64 : SchedWriteRes<[HWPort1, HWPort6]> {
let Latency = 3;
let NumMicroOps = 2;
}
+def : InstRW<[WriteMul64], (instregex "IMUL64r", "MUL64r")>;
+
+// m64.
def WriteMul64Ld : SchedWriteRes<[HWPort1, HWPort6, HWPort23]> {
let Latency = 7;
let NumMicroOps = 3;
}
-def : InstRW<[WriteMul64], (instregex "IMUL64r", "MUL64r")>;
def : InstRW<[WriteMul64Ld], (instregex "IMUL64m", "MUL64m")>;
+// r16,r16.
def WriteMul16rri : SchedWriteRes<[HWPort1, HWPort0156]> {
let Latency = 4;
let NumMicroOps = 2;
}
+def : InstRW<[WriteMul16rri], (instregex "IMUL16rri", "IMUL16rri8")>;
+
+// r16,m16.
def WriteMul16rmi : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> {
let Latency = 8;
let NumMicroOps = 3;
}
-def : InstRW<[WriteMul16rri], (instregex "IMUL16rri", "IMUL16rri8")>;
def : InstRW<[WriteMul16rmi], (instregex "IMUL16rmi", "IMUL16rmi8")>;
// MULX.
+// r32,r32,r32.
def WriteMulX32 : SchedWriteRes<[HWPort1, HWPort056]> {
let Latency = 4;
let NumMicroOps = 3;
let ResourceCycles = [1, 2];
}
+def : InstRW<[WriteMulX32], (instregex "MULX32rr")>;
+
+// r32,r32,m32.
def WriteMulX32Ld : SchedWriteRes<[HWPort1, HWPort056, HWPort23]> {
let Latency = 8;
let NumMicroOps = 4;
let ResourceCycles = [1, 2, 1];
}
-def : InstRW<[WriteMulX32], (instregex "MULX32rr")>;
def : InstRW<[WriteMulX32Ld], (instregex "MULX32rm")>;
+// r64,r64,r64.
def WriteMulX64 : SchedWriteRes<[HWPort1, HWPort6]> {
let Latency = 4;
let NumMicroOps = 2;
}
+def : InstRW<[WriteMulX64], (instregex "MULX64rr")>;
+
+// r64,r64,m64.
def WriteMulX64Ld : SchedWriteRes<[HWPort1, HWPort6, HWPort23]> {
let Latency = 8;
let NumMicroOps = 3;
}
-def : InstRW<[WriteMulX64], (instregex "MULX64rr")>;
def : InstRW<[WriteMulX64Ld], (instregex "MULX64rm")>;
// DIV.
+// r8.
def WriteDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
let Latency = 22;
let NumMicroOps = 9;
}
def : InstRW<[WriteDiv8], (instregex "DIV8r")>;
+// r16.
def WriteDiv16 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
let Latency = 23;
let NumMicroOps = 10;
}
def : InstRW<[WriteDiv16], (instregex "DIV16r")>;
+// r32.
def WriteDiv32 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
let Latency = 22;
let NumMicroOps = 10;
}
def : InstRW<[WriteDiv32], (instregex "DIV32r")>;
+// r64.
def WriteDiv64 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
let Latency = 32;
let NumMicroOps = 36;
}
def : InstRW<[WriteDiv64], (instregex "DIV64r")>;
+// IDIV.
+// r8.
def WriteIDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
let Latency = 23;
let NumMicroOps = 9;
}
def : InstRW<[WriteIDiv8], (instregex "IDIV8r")>;
+// r16.
def WriteIDiv16 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
let Latency = 23;
let NumMicroOps = 10;
}
def : InstRW<[WriteIDiv16], (instregex "IDIV16r")>;
+// r32.
def WriteIDiv32 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
let Latency = 22;
let NumMicroOps = 9;
}
def : InstRW<[WriteIDiv32], (instregex "IDIV32r")>;
+// r64.
def WriteIDiv64 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
let Latency = 39;
let NumMicroOps = 59;
def : InstRW<[WriteIDiv64], (instregex "IDIV64r")>;
//-- Logic instructions --//
+
// AND OR XOR.
-def : InstRW<[Write2ALUStore2Addr1Data],
+// m,r/i.
+def : InstRW<[Write2P0156_2P237_P4],
(instregex "(AND|OR|XOR)(8|16|32|64)m(r|i)",
"(AND|OR|XOR)(8|16|32|64)mi8", "(AND|OR|XOR)64mi32")>;
-
// SHR SHL SAR.
+// m,i.
def WriteShiftRMW : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
let NumMicroOps = 4;
let ResourceCycles = [2, 1, 1];
}
def : InstRW<[WriteShiftRMW], (instregex "S(A|H)(R|L)(8|16|32|64)m(i|1)")>;
-def : InstRW<[Write3Shift], (instregex "S(A|H)(R|L)(8|16|32|64)rCL")>;
+// r,cl.
+def : InstRW<[Write3P06_Lat2], (instregex "S(A|H)(R|L)(8|16|32|64)rCL")>;
+// m,cl.
def WriteShiftClLdRMW : SchedWriteRes<[HWPort06, HWPort23, HWPort4]> {
let NumMicroOps = 6;
let ResourceCycles = [3, 2, 1];
def : InstRW<[WriteShiftClLdRMW], (instregex "S(A|H)(R|L)(8|16|32|64)mCL")>;
// ROR ROL.
-def : InstRW<[Write2Shift], (instregex "RO(R|L)(8|16|32|64)r1")>;
+// r,1.
+def : InstRW<[Write2P06], (instregex "RO(R|L)(8|16|32|64)r1")>;
+// m,i.
def WriteRotateRMW : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
let NumMicroOps = 5;
let ResourceCycles = [2, 2, 1];
}
def : InstRW<[WriteRotateRMW], (instregex "RO(R|L)(8|16|32|64)mi")>;
-def : InstRW<[Write3Shift], (instregex "RO(R|L)(8|16|32|64)rCL")>;
+// r,cl.
+def : InstRW<[Write3P06_Lat2], (instregex "RO(R|L)(8|16|32|64)rCL")>;
+// m,cl.
def WriteRotateRMWCL : SchedWriteRes<[]> {
let NumMicroOps = 6;
}
def : InstRW<[WriteRotateRMWCL], (instregex "RO(R|L)(8|16|32|64)mCL")>;
// RCR RCL.
+// r,1.
def WriteRCr1 : SchedWriteRes<[HWPort06, HWPort0156]> {
let Latency = 2;
let NumMicroOps = 3;
}
def : InstRW<[WriteRCr1], (instregex "RC(R|L)(8|16|32|64)r1")>;
+// m,1.
def WriteRCm1 : SchedWriteRes<[]> {
let NumMicroOps = 6;
}
def : InstRW<[WriteRCm1], (instregex "RC(R|L)(8|16|32|64)m1")>;
+// r,i.
def WriteRCri : SchedWriteRes<[HWPort0156]> {
let Latency = 6;
let NumMicroOps = 8;
}
def : InstRW<[WriteRCri], (instregex "RC(R|L)(8|16|32|64)r(i|CL)")>;
+// m,i.
def WriteRCmi : SchedWriteRes<[]> {
let NumMicroOps = 11;
}
def : InstRW<[WriteRCmi], (instregex "RC(R|L)(8|16|32|64)m(i|CL)")>;
// SHRD SHLD.
+// r,r,i.
def WriteShDrr : SchedWriteRes<[HWPort1]> {
let Latency = 3;
}
def : InstRW<[WriteShDrr], (instregex "SH(R|L)D(16|32|64)rri8")>;
+// m,r,i.
def WriteShDmr : SchedWriteRes<[]> {
let NumMicroOps = 5;
}
def : InstRW<[WriteShDmr], (instregex "SH(R|L)D(16|32|64)mri8")>;
+// r,r,cl.
def WriteShlDCL : SchedWriteRes<[HWPort0156]> {
let Latency = 3;
let NumMicroOps = 4;
}
def : InstRW<[WriteShlDCL], (instregex "SHLD(16|32|64)rrCL")>;
+// r,r,cl.
def WriteShrDCL : SchedWriteRes<[HWPort0156]> {
let Latency = 4;
let NumMicroOps = 4;
}
def : InstRW<[WriteShrDCL], (instregex "SHRD(16|32|64)rrCL")>;
+// m,r,cl.
def WriteShDmrCL : SchedWriteRes<[]> {
let NumMicroOps = 7;
}
def : InstRW<[WriteShDmrCL], (instregex "SH(R|L)D(16|32|64)mrCL")>;
// BT.
+// r,r/i.
def : InstRW<[WriteShift], (instregex "BT(16|32|64)r(r|i8)")>;
+// m,r.
def WriteBTmr : SchedWriteRes<[]> {
let NumMicroOps = 10;
}
def : InstRW<[WriteBTmr], (instregex "BT(16|32|64)mr")>;
+// m,i.
def : InstRW<[WriteShiftLd], (instregex "BT(16|32|64)mi8")>;
// BTR BTS BTC.
+// r,r,i.
def : InstRW<[WriteShift], (instregex "BT(R|S|C)(16|32|64)r(r|i8)")>;
+// m,r.
def WriteBTRSCmr : SchedWriteRes<[]> {
let NumMicroOps = 11;
}
def : InstRW<[WriteBTRSCmr], (instregex "BT(R|S|C)(16|32|64)mr")>;
+// m,i.
def : InstRW<[WriteShiftLd], (instregex "BT(R|S|C)(16|32|64)mi8")>;
// BSF BSR.
-def : InstRW<[WriteP1Lat3], (instregex "BS(R|F)(16|32|64)rr")>;
-def : InstRW<[WriteP1Lat3Ld], (instregex "BS(R|F)(16|32|64)rm")>;
+// r,r.
+def : InstRW<[WriteP1_Lat3], (instregex "BS(R|F)(16|32|64)rr")>;
+// r,m.
+def : InstRW<[WriteP1_Lat3Ld], (instregex "BS(R|F)(16|32|64)rm")>;
// SETcc.
+// r.
def : InstRW<[WriteShift],
(instregex "SET(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)r")>;
+// m.
def WriteSetCCm : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
let NumMicroOps = 3;
}
}
def : InstRW<[WriteCldStd], (instregex "STD", "CLD")>;
-//LZCNT TZCNT.
-def : InstRW<[WriteP1Lat3], (instregex "(L|TZCNT)(16|32|64)rr")>;
-def : InstRW<[WriteP1Lat3Ld], (instregex "(L|TZCNT)(16|32|64)rm")>;
+// LZCNT TZCNT.
+// r,r.
+def : InstRW<[WriteP1_Lat3], (instregex "(L|TZCNT)(16|32|64)rr")>;
+// r,m.
+def : InstRW<[WriteP1_Lat3Ld], (instregex "(L|TZCNT)(16|32|64)rm")>;
// ANDN.
+// r,r.
def : InstRW<[WriteP15], (instregex "ANDN(32|64)rr")>;
+// r,m.
def : InstRW<[WriteP15Ld], (instregex "ANDN(32|64)rm")>;
// BLSI BLSMSK BLSR.
+// r,r.
def : InstRW<[WriteP15], (instregex "BLS(I|MSK|R)(32|64)rr")>;
+// r,m.
def : InstRW<[WriteP15Ld], (instregex "BLS(I|MSK|R)(32|64)rm")>;
// BEXTR.
-def : InstRW<[Write2ALU], (instregex "BEXTR(32|64)rr")>;
-def : InstRW<[Write2ALULd], (instregex "BEXTR(32|64)rm")>;
+// r,r,r.
+def : InstRW<[Write2P0156_Lat2], (instregex "BEXTR(32|64)rr")>;
+// r,m,r.
+def : InstRW<[Write2P0156_Lat2Ld], (instregex "BEXTR(32|64)rm")>;
// BZHI.
+// r,r,r.
def : InstRW<[WriteP15], (instregex "BZHI(32|64)rr")>;
+// r,m,r.
def : InstRW<[WriteP15Ld], (instregex "BZHI(32|64)rm")>;
// PDEP PEXT.
-def : InstRW<[WriteP1Lat3], (instregex "PDEP(32|64)rr", "PEXT(32|64)rr")>;
-def : InstRW<[WriteP1Lat3Ld], (instregex "PDEP(32|64)rm", "PEXT(32|64)rm")>;
+// r,r,r.
+def : InstRW<[WriteP1_Lat3], (instregex "PDEP(32|64)rr", "PEXT(32|64)rr")>;
+// r,m,r.
+def : InstRW<[WriteP1_Lat3Ld], (instregex "PDEP(32|64)rm", "PEXT(32|64)rm")>;
//-- Control transfer instructions --//
+
// J(E|R)CXZ.
def WriteJCXZ : SchedWriteRes<[HWPort0156, HWPort6]> {
let NumMicroOps = 2;
def : InstRW<[WriteLOOPE], (instregex "LOOPE", "LOOPNE")>;
// CALL.
+// r.
def WriteCALLr : SchedWriteRes<[HWPort237, HWPort4, HWPort6]> {
let NumMicroOps = 3;
}
def : InstRW<[WriteCALLr], (instregex "CALL(16|32)r")>;
+// m.
def WriteCALLm : SchedWriteRes<[HWPort237, HWPort4, HWPort6]> {
let NumMicroOps = 4;
let ResourceCycles = [2, 1, 1];
}
def : InstRW<[WriteRET], (instregex "RET(L|Q|W)", "LRET(L|Q|W)")>;
+// i.
def WriteRETI : SchedWriteRes<[HWPort23, HWPort6, HWPort015]> {
let NumMicroOps = 4;
let ResourceCycles = [1, 2, 1];
def : InstRW<[WriteRETI], (instregex "RETI(L|Q|W)", "LRETI(L|Q|W)")>;
// BOUND.
+// r,m.
def WriteBOUND : SchedWriteRes<[]> {
let NumMicroOps = 15;
}
}
def : InstRW<[WriteINTO], (instregex "INTO")>;
-
//-- String instructions --//
+
// LODSB/W.
def : InstRW<[Write2P0156_P23], (instregex "LODS(B|W)")>;
def : InstRW<[WriteCMPS], (instregex "CMPS(B|L|Q|W)")>;
//-- Synchronization instructions --//
+
// XADD.
-def WriteXADD : SchedWriteRes<[HWPort237, HWPort6, HWPort0156]> {
- let Latency = 7;
+def WriteXADD : SchedWriteRes<[]> {
let NumMicroOps = 5;
}
def : InstRW<[WriteXADD], (instregex "XADD(8|16|32|64)rm")>;
// CMPXCHG.
-def WriteCMPXCHG : SchedWriteRes<[HWPort237, HWPort6, HWPort0156]> {
- let Latency = 6;
- let NumMicroOps = 9;
+def WriteCMPXCHG : SchedWriteRes<[]> {
+ let NumMicroOps = 6;
}
def : InstRW<[WriteCMPXCHG], (instregex "CMPXCHG(8|16|32|64)rm")>;
// CMPXCHG8B.
-def WriteCMPXCHG8B : SchedWriteRes<[HWPort237, HWPort6, HWPort0156]> {
- let Latency = 9;
- let NumMicroOps = 16;
+def WriteCMPXCHG8B : SchedWriteRes<[]> {
+ let NumMicroOps = 15;
}
def : InstRW<[WriteCMPXCHG8B], (instregex "CMPXCHG8B")>;
// CMPXCHG16B.
-def WriteCMPXCHG16B : SchedWriteRes<[HWPort237, HWPort6, HWPort0156]> {
- let Latency = 15;
+def WriteCMPXCHG16B : SchedWriteRes<[]> {
let NumMicroOps = 22;
}
def : InstRW<[WriteCMPXCHG16B], (instregex "CMPXCHG16B")>;
//-- Other --//
+
// PAUSE.
def WritePAUSE : SchedWriteRes<[HWPort05, HWPort6]> {
let NumMicroOps = 5;
//=== Floating Point x87 Instructions ===//
//-- Move instructions --//
+
// FLD.
+// m80.
def : InstRW<[WriteP01], (instregex "LD_Frr")>;
def WriteLD_F80m : SchedWriteRes<[HWPort01, HWPort23]> {
def : InstRW<[WriteLD_F80m], (instregex "LD_F80m")>;
// FBLD.
+// m80.
def WriteFBLD : SchedWriteRes<[]> {
let Latency = 47;
let NumMicroOps = 43;
def : InstRW<[WriteFBLD], (instregex "FBLDm")>;
// FST(P).
+// r.
def : InstRW<[WriteP01], (instregex "ST_(F|FP)rr")>;
+// m80.
def WriteST_FP80m : SchedWriteRes<[HWPort0156, HWPort23, HWPort4]> {
let NumMicroOps = 7;
let ResourceCycles = [3, 2, 2];
def : InstRW<[WriteST_FP80m], (instregex "ST_FP80m")>;
// FBSTP.
+// m80.
def WriteFBSTP : SchedWriteRes<[]> {
let NumMicroOps = 226;
}
def : InstRW<[WriteFCMOVcc], (instregex "CMOV(B|BE|P|NB|NBE|NE|NP)_F")>;
// FNSTSW.
+// AX.
def WriteFNSTSW : SchedWriteRes<[HWPort0, HWPort0156]> {
let NumMicroOps = 2;
}
def : InstRW<[WriteFNSTSW], (instregex "FNSTSW16r")>;
+// m16.
def WriteFNSTSWm : SchedWriteRes<[HWPort0, HWPort4, HWPort237]> {
let Latency = 6;
let NumMicroOps = 3;
def : InstRW<[WriteFRSTOR], (instregex "FRSTORm")>;
//-- Arithmetic instructions --//
+
// FABS.
def : InstRW<[WriteP0], (instregex "ABS_F")>;
def : InstRW<[WriteP0], (instregex "CHS_F")>;
// FCOM(P) FUCOM(P).
+// r.
def : InstRW<[WriteP1], (instregex "COM_FST0r", "COMP_FST0r", "UCOM_Fr",
"UCOM_FPr")>;
+// m.
def : InstRW<[WriteP1_P23], (instregex "FCOM(32|64)m", "FCOMP(32|64)m")>;
// FCOMPP FUCOMPP.
+// r.
def : InstRW<[Write2P01], (instregex "FCOMPP", "UCOM_FPPr")>;
// FCOMI(P) FUCOMI(P).
+// m.
def : InstRW<[Write3P01], (instregex "COM_FIr", "COM_FIPr", "UCOM_FIr",
"UCOM_FIPr")>;
def : InstRW<[WriteFRNDINT], (instregex "FRNDINT")>;
//-- Math instructions --//
+
// FSCALE.
def WriteFSCALE : SchedWriteRes<[]> {
let Latency = 75; // 49-125
def : InstRW<[WriteFXTRACT], (instregex "FXTRACT")>;
//-- Other instructions --//
+
// FNOP.
def : InstRW<[WriteP01], (instregex "FNOP")>;
//=== Integer MMX and XMM Instructions ===//
//-- Move instructions --//
+
// MOVD.
// r32/64 <- (x)mm.
def : InstRW<[WriteP0], (instregex "MMX_MOVD64grr", "MMX_MOVD64from64rr",
"VMOVDQ(A|U)Yrr", "VMOVDQ(A|U)Yrr_REV")>;
// MOVDQ2Q.
-def : InstRW<[WriteP01P5], (instregex "MMX_MOVDQ2Qrr")>;
+def : InstRW<[WriteP01_P5], (instregex "MMX_MOVDQ2Qrr")>;
// MOVQ2DQ.
def : InstRW<[WriteP015], (instregex "MMX_MOVQ2DQrr")>;
}
def : InstRW<[WriteVPMOVSX], (instregex "VPMOV(SX|ZX)(BW|BQ|DW|DQ)Yrr")>;
+// PBLENDW.
+// x,x,i / v,v,v,i
+def WritePBLENDWr : SchedWriteRes<[HWPort5]>;
+def : InstRW<[WritePBLENDWr], (instregex "(V?)PBLENDW(Y?)rri")>;
+
+// x,m,i / v,v,m,i
+def WritePBLENDWm : SchedWriteRes<[HWPort5, HWPort23]> {
+ let NumMicroOps = 2;
+ let Latency = 4;
+ let ResourceCycles = [1, 1];
+}
+def : InstRW<[WritePBLENDWm, ReadAfterLd], (instregex "(V?)PBLENDW(Y?)rmi")>;
+
+// VPBLENDD.
+// v,v,v,i.
+def WriteVPBLENDDr : SchedWriteRes<[HWPort015]>;
+def : InstRW<[WriteVPBLENDDr], (instregex "VPBLENDD(Y?)rri")>;
+
+// v,v,m,i
+def WriteVPBLENDDm : SchedWriteRes<[HWPort015, HWPort23]> {
+ let NumMicroOps = 2;
+ let Latency = 4;
+ let ResourceCycles = [1, 1];
+}
+def : InstRW<[WriteVPBLENDDm, ReadAfterLd], (instregex "VPBLENDD(Y?)rmi")>;
+
+// MASKMOVQ.
+def WriteMASKMOVQ : SchedWriteRes<[HWPort0, HWPort4, HWPort23]> {
+ let Latency = 13;
+ let NumMicroOps = 4;
+ let ResourceCycles = [1, 1, 2];
+}
+def : InstRW<[WriteMASKMOVQ], (instregex "MMX_MASKMOVQ(64)?")>;
+
+// MASKMOVDQU.
+def WriteMASKMOVDQU : SchedWriteRes<[HWPort04, HWPort56, HWPort23]> {
+ let Latency = 14;
+ let NumMicroOps = 10;
+ let ResourceCycles = [4, 2, 4];
+}
+def : InstRW<[WriteMASKMOVDQU], (instregex "(V?)MASKMOVDQU(64)?")>;
+
+// VPMASKMOV D/Q.
+// v,v,m.
+def WriteVPMASKMOVr : SchedWriteRes<[HWPort5, HWPort23]> {
+ let Latency = 4;
+ let NumMicroOps = 3;
+ let ResourceCycles = [2, 1];
+}
+def : InstRW<[WriteVPMASKMOVr, ReadAfterLd],
+ (instregex "VPMASKMOV(D|Q)(Y?)rm")>;
+
+// m, v,v.
+def WriteVPMASKMOVm : SchedWriteRes<[HWPort0, HWPort1, HWPort4, HWPort23]> {
+ let Latency = 13;
+ let NumMicroOps = 4;
+ let ResourceCycles = [1, 1, 1, 1];
+}
+def : InstRW<[WriteVPMASKMOVm], (instregex "VPMASKMOV(D|Q)(Y?)mr")>;
+
+// PMOVMSKB.
+def WritePMOVMSKB : SchedWriteRes<[HWPort0]> {
+ let Latency = 3;
+}
+def : InstRW<[WritePMOVMSKB], (instregex "(V|MMX_)?PMOVMSKB(Y?)rr")>;
+
+// PEXTR B/W/D/Q.
+// r32,x,i.
+def WritePEXTRr : SchedWriteRes<[HWPort0, HWPort5]> {
+ let Latency = 2;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1, 1];
+}
+def : InstRW<[WritePEXTRr], (instregex "PEXTR(B|W|D|Q)rr", "MMX_PEXTRWirri")>;
+
+// m8,x,i.
+def WritePEXTRm : SchedWriteRes<[HWPort23, HWPort4, HWPort5]> {
+ let NumMicroOps = 3;
+ let ResourceCycles = [1, 1, 1];
+}
+def : InstRW<[WritePEXTRm], (instregex "PEXTR(B|W|D|Q)mr")>;
+
+// VPBROADCAST B/W.
+// x, m8/16.
+def WriteVPBROADCAST128Ld : SchedWriteRes<[HWPort01, HWPort23, HWPort5]> {
+ let Latency = 5;
+ let NumMicroOps = 3;
+ let ResourceCycles = [1, 1, 1];
+}
+def : InstRW<[WriteVPBROADCAST128Ld, ReadAfterLd],
+ (instregex "VPBROADCAST(B|W)rm")>;
+
+// y, m8/16
+def WriteVPBROADCAST256Ld : SchedWriteRes<[HWPort01, HWPort23, HWPort5]> {
+ let Latency = 7;
+ let NumMicroOps = 3;
+ let ResourceCycles = [1, 1, 1];
+}
+def : InstRW<[WriteVPBROADCAST256Ld, ReadAfterLd],
+ (instregex "VPBROADCAST(B|W)Yrm")>;
+
+// VPGATHERDD.
+// x.
+def WriteVPGATHERDD128 : SchedWriteRes<[]> {
+ let NumMicroOps = 20;
+}
+def : InstRW<[WriteVPGATHERDD128, ReadAfterLd], (instregex "VPGATHERDDrm")>;
+
+// y.
+def WriteVPGATHERDD256 : SchedWriteRes<[]> {
+ let NumMicroOps = 34;
+}
+def : InstRW<[WriteVPGATHERDD256, ReadAfterLd], (instregex "VPGATHERDDYrm")>;
+
+// VPGATHERQD.
+// x.
+def WriteVPGATHERQD128 : SchedWriteRes<[]> {
+ let NumMicroOps = 15;
+}
+def : InstRW<[WriteVPGATHERQD128, ReadAfterLd], (instregex "VPGATHERQDrm")>;
+
+// y.
+def WriteVPGATHERQD256 : SchedWriteRes<[]> {
+ let NumMicroOps = 22;
+}
+def : InstRW<[WriteVPGATHERQD256, ReadAfterLd], (instregex "VPGATHERQDYrm")>;
+
+// VPGATHERDQ.
+// x.
+def WriteVPGATHERDQ128 : SchedWriteRes<[]> {
+ let NumMicroOps = 12;
+}
+def : InstRW<[WriteVPGATHERDQ128, ReadAfterLd], (instregex "VPGATHERDQrm")>;
+
+// y.
+def WriteVPGATHERDQ256 : SchedWriteRes<[]> {
+ let NumMicroOps = 20;
+}
+def : InstRW<[WriteVPGATHERDQ256, ReadAfterLd], (instregex "VPGATHERDQYrm")>;
+
+// VPGATHERQQ.
+// x.
+def WriteVPGATHERQQ128 : SchedWriteRes<[]> {
+ let NumMicroOps = 14;
+}
+def : InstRW<[WriteVPGATHERQQ128, ReadAfterLd], (instregex "VPGATHERQQrm")>;
+
+// y.
+def WriteVPGATHERQQ256 : SchedWriteRes<[]> {
+ let NumMicroOps = 22;
+}
+def : InstRW<[WriteVPGATHERQQ256, ReadAfterLd], (instregex "VPGATHERQQYrm")>;
} // SchedModel
projects / oota-llvm.git / blobdiff