def Port1 : FuncUnit; // ALU: ALU1, bit processing, jump, and LEA
// SIMD/FP: SIMD ALU, FP Adder
-def AtomItineraries : MultiIssueItineraries<
- 2, // IssueWidth=2 allows 2 instructions per scheduling group.
- 1, // MinLatency=1. InstrStage cycles overrides MinLatency.
- // OperandCycles may be used for expected latency.
- 3, // LoadLatency (expected, may be overriden by OperandCycles)
- 30,// HighLatency (expected, may be overriden by OperandCycles)
+def AtomItineraries : ProcessorItineraries<
[ Port0, Port1 ],
[], [
// P0 only
InstrItinData<IIC_NOP, [InstrStage<1, [Port0, Port1]>] >
]>;
+// Atom machine model.
+def AtomModel : SchedMachineModel {
+ let IssueWidth = 2; // Allows 2 instructions per scheduling group.
+ let MinLatency = 1; // InstrStage cycles overrides MinLatency.
+ // OperandCycles may be used for expected latency.
+ let LoadLatency = 3; // Expected cycles, may be overriden by OperandCycles.
+ let HighLatency = 30;// Expected, may be overriden by OperandCycles.
+
+ let Itineraries = AtomItineraries;
+}