#include "X86TargetMachine.h"
#include "X86.h"
-#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/PassManager.h"
#include "llvm/Support/CommandLine.h"
extern "C" void LLVMInitializeX86Target() {
// Register the target.
- RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target);
- RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target);
+ RegisterTargetMachine<X86TargetMachine> X(TheX86_32Target);
+ RegisterTargetMachine<X86TargetMachine> Y(TheX86_64Target);
}
-void X86_32TargetMachine::anchor() { }
+void X86TargetMachine::anchor() { }
static std::string computeDataLayout(const X86Subtarget &ST) {
// X86 is little endian
std::string Ret = "e";
+ Ret += DataLayout::getManglingComponent(ST.getTargetTriple());
// X86 and x32 have 32 bit pointers.
if (ST.isTarget64BitILP32() || !ST.is64Bit())
Ret += "-p:32:32";
else
Ret += "-f80:32";
- // Objects on the stack ore aligned to 64 bits.
- if (ST.is64Bit())
- Ret += "-s:64";
-
// The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
if (ST.is64Bit())
Ret += "-n8:16:32:64";
return Ret;
}
-X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
- StringRef CPU, StringRef FS,
- const TargetOptions &Options,
- Reloc::Model RM, CodeModel::Model CM,
- CodeGenOpt::Level OL)
- : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false),
- DL(computeDataLayout(*getSubtargetImpl())),
- InstrInfo(*this),
- TLInfo(*this),
- TSInfo(*this),
- JITInfo(*this) {
- initAsmInfo();
-}
-
-void X86_64TargetMachine::anchor() { }
-
-X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
- StringRef CPU, StringRef FS,
- const TargetOptions &Options,
- Reloc::Model RM, CodeModel::Model CM,
- CodeGenOpt::Level OL)
- : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true),
- // The x32 ABI dictates the ILP32 programming model for x64.
- DL(computeDataLayout(*getSubtargetImpl())),
- InstrInfo(*this),
- TLInfo(*this),
- TSInfo(*this),
- JITInfo(*this) {
- initAsmInfo();
-}
-
/// X86TargetMachine ctor - Create an X86 target.
///
X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
- CodeGenOpt::Level OL,
- bool is64Bit)
+ CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
- Subtarget(TT, CPU, FS, Options.StackAlignmentOverride, is64Bit),
+ Subtarget(TT, CPU, FS, Options.StackAlignmentOverride),
FrameLowering(*this, Subtarget),
- InstrItins(Subtarget.getInstrItineraryData()){
+ InstrItins(Subtarget.getInstrItineraryData()),
+ DL(computeDataLayout(*getSubtargetImpl())),
+ InstrInfo(*this),
+ TLInfo(*this),
+ TSInfo(*this),
+ JITInfo(*this) {
// Determine the PICStyle based on the target selected.
if (getRelocationModel() == Reloc::Static) {
// Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
// default to hard float ABI
if (Options.FloatABIType == FloatABI::Default)
this->Options.FloatABIType = FloatABI::Hard;
+
+ initAsmInfo();
}
//===----------------------------------------------------------------------===//
return *getX86TargetMachine().getSubtargetImpl();
}
- virtual bool addInstSelector();
- virtual bool addILPOpts();
- virtual bool addPreRegAlloc();
- virtual bool addPostRegAlloc();
- virtual bool addPreEmitPass();
+ bool addInstSelector() override;
+ bool addILPOpts() override;
+ bool addPreRegAlloc() override;
+ bool addPostRegAlloc() override;
+ bool addPreEmitPass() override;
};
} // namespace