Change llc command line for register allocators

[oota-llvm.git] / lib / Target / X86 / X86TargetMachine.cpp

diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp
index 9137f6befc9ac26c14b728dd7f64044be46f96c4..8f6829f6de4ad49341048714df9e58e013257e98 100644 (file)
--- a/lib/Target/X86/X86TargetMachine.cpp
+++ b/lib/Target/X86/X86TargetMachine.cpp
@@ -6,6 +6,7 @@
 
 #include "X86TargetMachine.h"
 #include "X86.h"
+#include "llvm/Module.h"
 #include "llvm/PassManager.h"
 #include "llvm/Target/TargetMachineImpls.h"
 #include "llvm/CodeGen/MachineFunction.h"
@@ -13,43 +14,92 @@
 #include "llvm/Transforms/Scalar.h"
 #include "Support/CommandLine.h"
 #include "Support/Statistic.h"
-#include <iostream>
 
 namespace {
-  cl::opt<bool> NoLocalRA("disable-local-ra",
-                          cl::desc("Use Simple RA instead of Local RegAlloc"));
+  cl::opt<RegAllocName>
+  RegAlloc("regalloc",
+           cl::desc("Register allocator to use: (default = simple)"),
+           cl::Prefix,
+           cl::values(clEnumVal(simple, "  simple register allocator"),
+                      clEnumVal(local,  "  local register allocator"),
+                      0),
+           cl::init(local));
+
   cl::opt<bool> PrintCode("print-machineinstrs",
                          cl::desc("Print generated machine code"));
+  cl::opt<bool> NoPatternISel("disable-pattern-isel", cl::init(true),
+                        cl::desc("Use the 'simple' X86 instruction selector"));
 }
 
 // allocateX86TargetMachine - Allocate and return a subclass of TargetMachine
 // that implements the X86 backend.
 //
-TargetMachine *allocateX86TargetMachine(unsigned Configuration) {
-  return new X86TargetMachine(Configuration);
+TargetMachine *allocateX86TargetMachine(const Module &M) {
+  return new X86TargetMachine(M);
 }
 
 
 /// X86TargetMachine ctor - Create an ILP32 architecture model
 ///
-X86TargetMachine::X86TargetMachine(unsigned Config)
+X86TargetMachine::X86TargetMachine(const Module &M)
   : TargetMachine("X86", 
-                 (Config & TM::EndianMask) == TM::LittleEndian,
-                 (Config & TM::PtrSizeMask) == TM::PtrSize64 ? 8 : 4,
-                 (Config & TM::PtrSizeMask) == TM::PtrSize64 ? 8 : 4,
-                 (Config & TM::PtrSizeMask) == TM::PtrSize64 ? 8 : 4),
-  FrameInfo(TargetFrameInfo::StackGrowsDown, 8/*16 for SSE*/, 4) {
+                 M.getEndianness() != Module::BigEndian,
+                  M.getPointerSize() != Module::Pointer64 ? 4 : 8,
+                  M.getPointerSize() != Module::Pointer64 ? 4 : 8,
+                  M.getPointerSize() != Module::Pointer64 ? 4 : 8,
+                  4, M.getPointerSize() != Module::Pointer64 ? 4 : 8),
+    FrameInfo(TargetFrameInfo::StackGrowsDown, 8/*16 for SSE*/, 4) {
 }
 
-// llc backend for x86
+
+// addPassesToEmitAssembly - We currently use all of the same passes as the JIT
+// does to emit statically compiled machine code.
 bool X86TargetMachine::addPassesToEmitAssembly(PassManager &PM,
                                               std::ostream &Out) {
+  // FIXME: Implement the switch instruction in the instruction selector!
   PM.add(createLowerSwitchPass());
-  PM.add(createSimpleX86InstructionSelector(*this));
-  PM.add(createLocalRegisterAllocator());
+
+  if (NoPatternISel)
+    PM.add(createX86SimpleInstructionSelector(*this));
+  else
+    PM.add(createX86PatternInstructionSelector(*this));
+
+  // TODO: optional optimizations go here
+
+  // FIXME: Add SSA based peephole optimizer here.
+
+  // Print the instruction selected machine code...
+  if (PrintCode)
+    PM.add(createMachineFunctionPrinterPass());
+
+  // Perform register allocation to convert to a concrete x86 representation
+  switch (RegAlloc) {
+  case simple:
+    PM.add(createSimpleRegisterAllocator());
+    break;
+  case local:
+    PM.add(createLocalRegisterAllocator());
+    break;
+  default:
+    assert(0 && "no register allocator selected");
+  }
+
+  if (PrintCode)
+    PM.add(createMachineFunctionPrinterPass());
+
   PM.add(createX86FloatingPointStackifierPass());
+
+  if (PrintCode)
+    PM.add(createMachineFunctionPrinterPass());
+
+  // Insert prolog/epilog code.  Eliminate abstract frame index references...
   PM.add(createPrologEpilogCodeInserter());
+
   PM.add(createX86PeepholeOptimizerPass());
+
+  if (PrintCode)  // Print the register-allocated code
+    PM.add(createX86CodePrinterPass(std::cerr, *this));
+
   PM.add(createX86CodePrinterPass(Out, *this));
   return false; // success!
 }
@@ -58,11 +108,14 @@ bool X86TargetMachine::addPassesToEmitAssembly(PassManager &PM,
 /// implement a fast dynamic compiler for this target.  Return true if this is
 /// not supported for this target.
 ///
-bool X86TargetMachine::addPassesToJITCompile(PassManager &PM) {
+bool X86TargetMachine::addPassesToJITCompile(FunctionPassManager &PM) {
   // FIXME: Implement the switch instruction in the instruction selector!
   PM.add(createLowerSwitchPass());
 
-  PM.add(createSimpleX86InstructionSelector(*this));
+  if (NoPatternISel)
+    PM.add(createX86SimpleInstructionSelector(*this));
+  else
+    PM.add(createX86PatternInstructionSelector(*this));
 
   // TODO: optional optimizations go here
 
@@ -73,10 +126,16 @@ bool X86TargetMachine::addPassesToJITCompile(PassManager &PM) {
     PM.add(createMachineFunctionPrinterPass());
 
   // Perform register allocation to convert to a concrete x86 representation
-  if (NoLocalRA)
+  switch (RegAlloc) {
+  case simple:
     PM.add(createSimpleRegisterAllocator());
-  else
+    break;
+  case local:
     PM.add(createLocalRegisterAllocator());
+    break;
+  default:
+    assert(0 && "no register allocator selected");
+  }
 
   if (PrintCode)
     PM.add(createMachineFunctionPrinterPass());
@@ -93,7 +152,6 @@ bool X86TargetMachine::addPassesToJITCompile(PassManager &PM) {
 
   if (PrintCode)  // Print the register-allocated code
     PM.add(createX86CodePrinterPass(std::cerr, *this));
-
   return false; // success!
 }