All store instructions really want 'rd' in the first field.

[oota-llvm.git] / lib / Target / X86 / X86TargetMachine.cpp

diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp
index 7d5e5ce4e96b822f214207d21c2edf1dc395f099..d5a628cb67085958998b75ca7582bd4843a5a090 100644 (file)
--- a/lib/Target/X86/X86TargetMachine.cpp
+++ b/lib/Target/X86/X86TargetMachine.cpp
@@ -5,52 +5,81 @@
 //===----------------------------------------------------------------------===//
 
 #include "X86TargetMachine.h"
-#include "llvm/Transforms/Scalar.h"
+#include "X86.h"
+#include "llvm/PassManager.h"
 #include "llvm/Target/TargetMachineImpls.h"
 #include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/PassManager.h"
-#include "X86.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/Transforms/Scalar.h"
+#include "Support/CommandLine.h"
+#include "Support/Statistic.h"
 #include <iostream>
 
+namespace {
+  cl::opt<bool> NoLocalRA("disable-local-ra",
+                          cl::desc("Use Simple RA instead of Local RegAlloc"));
+  cl::opt<bool> PrintCode("print-machineinstrs",
+                         cl::desc("Print generated machine code"));
+}
+
 // allocateX86TargetMachine - Allocate and return a subclass of TargetMachine
 // that implements the X86 backend.
 //
-TargetMachine *allocateX86TargetMachine() { return new X86TargetMachine(); }
+TargetMachine *allocateX86TargetMachine(unsigned Configuration) {
+  return new X86TargetMachine(Configuration);
+}
 
 
 /// X86TargetMachine ctor - Create an ILP32 architecture model
 ///
-X86TargetMachine::X86TargetMachine() : TargetMachine("X86", 1, 4, 4, 4) {
+X86TargetMachine::X86TargetMachine(unsigned Config)
+  : TargetMachine("X86", 
+                 (Config & TM::EndianMask) == TM::LittleEndian,
+                 (Config & TM::PtrSizeMask) == TM::PtrSize64 ? 8 : 4,
+                 (Config & TM::PtrSizeMask) == TM::PtrSize64 ? 8 : 4,
+                 (Config & TM::PtrSizeMask) == TM::PtrSize64 ? 8 : 4),
+  FrameInfo(TargetFrameInfo::StackGrowsDown, 8/*16 for SSE*/, 4) {
 }
 
-
 /// addPassesToJITCompile - Add passes to the specified pass manager to
 /// implement a fast dynamic compiler for this target.  Return true if this is
 /// not supported for this target.
 ///
 bool X86TargetMachine::addPassesToJITCompile(PassManager &PM) {
-  // For the moment we have decided that malloc and free will be
-  // taken care of by converting them to calls, using the existing
-  // LLVM scalar transforms pass to do this.
-  PM.add(createLowerAllocationsPass());
+  // FIXME: Implement the switch instruction in the instruction selector!
+  PM.add(createLowerSwitchPass());
 
   PM.add(createSimpleX86InstructionSelector(*this));
 
   // TODO: optional optimizations go here
 
+  // FIXME: Add SSA based peephole optimizer here.
+
   // Print the instruction selected machine code...
-  PM.add(createMachineFunctionPrinterPass());
+  if (PrintCode)
+    PM.add(createMachineFunctionPrinterPass());
 
   // Perform register allocation to convert to a concrete x86 representation
-  PM.add(createSimpleX86RegisterAllocator(*this));
+  if (NoLocalRA)
+    PM.add(createSimpleRegisterAllocator());
+  else
+    PM.add(createLocalRegisterAllocator());
 
-  // Print the instruction selected machine code...
-  // PM.add(createMachineFunctionPrinterPass());
+  if (PrintCode)
+    PM.add(createMachineFunctionPrinterPass());
+
+  PM.add(createX86FloatingPointStackifierPass());
+
+  if (PrintCode)
+    PM.add(createMachineFunctionPrinterPass());
+
+  // Insert prolog/epilog code.  Eliminate abstract frame index references...
+  PM.add(createPrologEpilogCodeInserter());
 
-  // Print the register-allocated code
-  PM.add(createX86CodePrinterPass(*this, std::cerr));
+  PM.add(createX86PeepholeOptimizerPass());
 
-  //PM.add(createEmitX86CodeToMemory(*this));
+  if (PrintCode)  // Print the register-allocated code
+    PM.add(createX86CodePrinterPass(std::cerr));
 
   return false; // success!
 }