#ifndef X86TARGETMACHINE_H
#define X86TARGETMACHINE_H
-#include "X86.h"
-#include "X86ELFWriterInfo.h"
-#include "X86InstrInfo.h"
-#include "X86ISelLowering.h"
#include "X86FrameLowering.h"
+#include "X86ISelLowering.h"
+#include "X86InstrInfo.h"
#include "X86JITInfo.h"
#include "X86SelectionDAGInfo.h"
#include "X86Subtarget.h"
+#include "llvm/IR/DataLayout.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetData.h"
-#include "llvm/Target/TargetFrameLowering.h"
namespace llvm {
-
-class formatted_raw_ostream;
+
class StringRef;
-class X86TargetMachine : public LLVMTargetMachine {
- X86Subtarget Subtarget;
- X86FrameLowering FrameLowering;
- X86ELFWriterInfo ELFWriterInfo;
+class X86TargetMachine final : public LLVMTargetMachine {
+ virtual void anchor();
+ X86Subtarget Subtarget;
+ X86FrameLowering FrameLowering;
+ InstrItineraryData InstrItins;
+ const DataLayout DL; // Calculates type size & alignment
+ X86InstrInfo InstrInfo;
+ X86TargetLowering TLInfo;
+ X86SelectionDAGInfo TSInfo;
+ X86JITInfo JITInfo;
-private:
- // We have specific defaults for X86.
- virtual void setCodeModelForJIT();
- virtual void setCodeModelForStatic();
-
public:
- X86TargetMachine(const Target &T, StringRef TT,
- StringRef CPU, StringRef FS,
- Reloc::Model RM, bool is64Bit);
+ X86TargetMachine(const Target &T, StringRef TT,
+ StringRef CPU, StringRef FS, const TargetOptions &Options,
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
- virtual const X86InstrInfo *getInstrInfo() const {
- llvm_unreachable("getInstrInfo not implemented");
+ const DataLayout *getDataLayout() const override { return &DL; }
+ const X86InstrInfo *getInstrInfo() const override {
+ return &InstrInfo;
}
- virtual const TargetFrameLowering *getFrameLowering() const {
+ const TargetFrameLowering *getFrameLowering() const override {
return &FrameLowering;
}
- virtual X86JITInfo *getJITInfo() {
- llvm_unreachable("getJITInfo not implemented");
+ X86JITInfo *getJITInfo() override {
+ return &JITInfo;
}
- virtual const X86Subtarget *getSubtargetImpl() const{ return &Subtarget; }
- virtual const X86TargetLowering *getTargetLowering() const {
- llvm_unreachable("getTargetLowering not implemented");
+ const X86Subtarget *getSubtargetImpl() const override { return &Subtarget; }
+ const X86TargetLowering *getTargetLowering() const override {
+ return &TLInfo;
}
- virtual const X86SelectionDAGInfo *getSelectionDAGInfo() const {
- llvm_unreachable("getSelectionDAGInfo not implemented");
+ const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
+ return &TSInfo;
}
- virtual const X86RegisterInfo *getRegisterInfo() const {
+ const X86RegisterInfo *getRegisterInfo() const override {
return &getInstrInfo()->getRegisterInfo();
}
- virtual const X86ELFWriterInfo *getELFWriterInfo() const {
- return Subtarget.isTargetELF() ? &ELFWriterInfo : 0;
+ const InstrItineraryData *getInstrItineraryData() const override {
+ return &InstrItins;
}
- // Set up the pass pipeline.
- virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
- virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
- virtual bool addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
- virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
- virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
- JITCodeEmitter &JCE);
-};
+ /// \brief Register X86 analysis passes with a pass manager.
+ void addAnalysisPasses(PassManagerBase &PM) override;
-/// X86_32TargetMachine - X86 32-bit target machine.
-///
-class X86_32TargetMachine : public X86TargetMachine {
- const TargetData DataLayout; // Calculates type size & alignment
- X86InstrInfo InstrInfo;
- X86SelectionDAGInfo TSInfo;
- X86TargetLowering TLInfo;
- X86JITInfo JITInfo;
-public:
- X86_32TargetMachine(const Target &T, StringRef TT,
- StringRef CPU, StringRef FS, Reloc::Model RM);
- virtual const TargetData *getTargetData() const { return &DataLayout; }
- virtual const X86TargetLowering *getTargetLowering() const {
- return &TLInfo;
- }
- virtual const X86SelectionDAGInfo *getSelectionDAGInfo() const {
- return &TSInfo;
- }
- virtual const X86InstrInfo *getInstrInfo() const {
- return &InstrInfo;
- }
- virtual X86JITInfo *getJITInfo() {
- return &JITInfo;
- }
-};
+ // Set up the pass pipeline.
+ TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
-/// X86_64TargetMachine - X86 64-bit target machine.
-///
-class X86_64TargetMachine : public X86TargetMachine {
- const TargetData DataLayout; // Calculates type size & alignment
- X86InstrInfo InstrInfo;
- X86SelectionDAGInfo TSInfo;
- X86TargetLowering TLInfo;
- X86JITInfo JITInfo;
-public:
- X86_64TargetMachine(const Target &T, StringRef TT,
- StringRef CPU, StringRef FS, Reloc::Model RM);
- virtual const TargetData *getTargetData() const { return &DataLayout; }
- virtual const X86TargetLowering *getTargetLowering() const {
- return &TLInfo;
- }
- virtual const X86SelectionDAGInfo *getSelectionDAGInfo() const {
- return &TSInfo;
- }
- virtual const X86InstrInfo *getInstrInfo() const {
- return &InstrInfo;
- }
- virtual X86JITInfo *getJITInfo() {
- return &JITInfo;
- }
+ bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE) override;
};
} // End llvm namespace