//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
#ifndef X86TARGETMACHINE_H
#define X86TARGETMACHINE_H
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetFrameInfo.h"
-#include "llvm/PassManager.h"
+#include "X86FrameLowering.h"
+#include "X86ISelLowering.h"
#include "X86InstrInfo.h"
#include "X86JITInfo.h"
#include "X86Subtarget.h"
+#include "llvm/IR/DataLayout.h"
+#include "llvm/Target/TargetMachine.h"
namespace llvm {
-class IntrinsicLowering;
-class X86TargetMachine : public TargetMachine {
- X86InstrInfo InstrInfo;
- X86Subtarget Subtarget;
- TargetFrameInfo FrameInfo;
- X86JITInfo JITInfo;
+class StringRef;
+
+class X86TargetMachine final : public LLVMTargetMachine {
+ virtual void anchor();
+ X86Subtarget Subtarget;
+
public:
- X86TargetMachine(const Module &M, IntrinsicLowering *IL);
-
- virtual const X86InstrInfo *getInstrInfo() const { return &InstrInfo; }
- virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; }
- virtual TargetJITInfo *getJITInfo() { return &JITInfo; }
- virtual const TargetSubtarget *getSubtargetImpl() const{ return &Subtarget; }
- virtual const MRegisterInfo *getRegisterInfo() const {
- return &InstrInfo.getRegisterInfo();
+ X86TargetMachine(const Target &T, StringRef TT,
+ StringRef CPU, StringRef FS, const TargetOptions &Options,
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
+
+ const DataLayout *getDataLayout() const override {
+ return getSubtargetImpl()->getDataLayout();
+ }
+ const X86InstrInfo *getInstrInfo() const override {
+ return getSubtargetImpl()->getInstrInfo();
+ }
+ const TargetFrameLowering *getFrameLowering() const override {
+ return getSubtargetImpl()->getFrameLowering();
+ }
+ X86JITInfo *getJITInfo() override { return Subtarget.getJITInfo(); }
+ const X86Subtarget *getSubtargetImpl() const override { return &Subtarget; }
+ const X86TargetLowering *getTargetLowering() const override {
+ return getSubtargetImpl()->getTargetLowering();
+ }
+ const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
+ return getSubtargetImpl()->getSelectionDAGInfo();
+ }
+ const X86RegisterInfo *getRegisterInfo() const override {
+ return &getInstrInfo()->getRegisterInfo();
+ }
+ const InstrItineraryData *getInstrItineraryData() const override {
+ return &getSubtargetImpl()->getInstrItineraryData();
}
- /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
- /// get machine code emitted. This uses a MachineCodeEmitter object to handle
- /// actually outputting the machine code and resolving things like the address
- /// of functions. This method should returns true if machine code emission is
- /// not supported.
- ///
- virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
- MachineCodeEmitter &MCE);
+ /// \brief Register X86 analysis passes with a pass manager.
+ void addAnalysisPasses(PassManagerBase &PM) override;
- virtual bool addPassesToEmitFile(PassManager &PM, std::ostream &Out,
- CodeGenFileType FileType);
+ // Set up the pass pipeline.
+ TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
- static unsigned getModuleMatchQuality(const Module &M);
- static unsigned getJITMatchQuality();
+ bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE) override;
};
+
} // End llvm namespace
#endif