Add instruction encodings / disassembly support for u6 / lu6 instructions.

[oota-llvm.git] / lib / Target / XCore / XCore.h

diff --git a/lib/Target/XCore/XCore.h b/lib/Target/XCore/XCore.h
index b7b86304b10e696b45eddee2c6d6d0cc596895f8..08f091e5b870198fe01feefd2c2d972c33164302 100644 (file)
--- a/lib/Target/XCore/XCore.h
+++ b/lib/Target/XCore/XCore.h
@@ -15,6 +15,7 @@
 #ifndef TARGET_XCORE_H
 #define TARGET_XCORE_H
 
+#include "MCTargetDesc/XCoreMCTargetDesc.h"
 #include "llvm/Target/TargetMachine.h"
 
 namespace llvm {
@@ -23,22 +24,9 @@ namespace llvm {
   class XCoreTargetMachine;
   class formatted_raw_ostream;
 
-  FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM);
-  FunctionPass *createXCoreCodePrinterPass(formatted_raw_ostream &OS,
-                                           TargetMachine &TM,
-                                           bool Verbose);
-
-  extern Target TheXCoreTarget;
+  FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM,
+                                   CodeGenOpt::Level OptLevel);
 
 } // end namespace llvm;
 
-// Defines symbolic names for XCore registers.  This defines a mapping from
-// register name to register number.
-//
-#include "XCoreGenRegisterNames.inc"
-
-// Defines symbolic names for the XCore instructions.
-//
-#include "XCoreGenInstrNames.inc"
-
 #endif