Add a option which would move ld/st multiple pass before post-alloc scheduling.

[oota-llvm.git] / lib / Target / XCore / XCoreInstrInfo.td

diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td
index 4ee1f63e638d5a4cc9f1cbccbad2c4b25a36d148..9d9cbf0e8e1d52d2b4e2af079916c0f0423a66ea 100644 (file)
--- a/lib/Target/XCore/XCoreInstrInfo.td
+++ b/lib/Target/XCore/XCoreInstrInfo.td
@@ -50,17 +50,17 @@ def SDT_XCoreAddress    : SDTypeProfile<1, 1,
                             [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
 
 def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress,
-                          []>;
+                           []>;
 
 def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress,
-                          []>;
+                           []>;
 
 def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress,
-                          []>;
+                           []>;
 
 def SDT_XCoreStwsp    : SDTypeProfile<0, 2, [SDTCisInt<1>]>;
-def XCoreStwsp         : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp,
-                          [SDNPHasChain]>;
+def XCoreStwsp        : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp,
+                               [SDNPHasChain]>;
 
 // These are target-independent nodes, but have target-specific formats.
 def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
@@ -95,6 +95,12 @@ def neg_xform : SDNodeXForm<imm, [{
   return getI32Imm(-value);
 }]>;
 
+def bpwsub_xform : SDNodeXForm<imm, [{
+  // Transformation function: 32-imm
+  uint32_t value = N->getZExtValue();
+  return getI32Imm(32-value);
+}]>;
+
 def div4neg_xform : SDNodeXForm<imm, [{
   // Transformation function: -imm/4
   uint32_t value = N->getZExtValue();
@@ -162,6 +168,14 @@ def immBitp : PatLeaf<(imm), [{
           || value == 32;
 }]>;
 
+def immBpwSubBitp : PatLeaf<(imm), [{
+  uint32_t value = (uint32_t)N->getZExtValue();
+  return (value >= 24 && value <= 31)
+          || value == 16
+          || value == 8
+          || value == 0;
+}]>;
+
 def lda16f : PatFrag<(ops node:$addr, node:$offset),
                      (add node:$addr, (shl node:$offset, 1))>;
 def lda16b : PatFrag<(ops node:$addr, node:$offset),
@@ -349,6 +363,18 @@ def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2),
                             [(callseq_end timm:$amt1, timm:$amt2)]>;
 }
 
+def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
+                             "${:comment} LDWFI $dst, $addr",
+                             [(set GRRegs:$dst, (load ADDRspii:$addr))]>;
+
+def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
+                             "${:comment} LDAWFI $dst, $addr",
+                             [(set GRRegs:$dst, ADDRspii:$addr)]>;
+
+def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr),
+                            "${:comment} STWFI $src, $addr",
+                            [(store GRRegs:$src, ADDRspii:$addr)]>;
+
 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation.  Expanded by the
 // scheduler into a branch sequence.
 let usesCustomDAGSchedInserter = 1 in {
@@ -543,51 +569,41 @@ let mayLoad = 1, isReMaterializable = 1 in
 defm LDWCP : FRU6_LRU6_cp<"ldw">;
 
 let Uses = [SP] in {
-let mayStore=1 in
+let mayStore=1 in {
 def STWSP_ru6 : _FRU6<
-                 (outs), (ins GRRegs:$dst, MEMii:$b),
-                 "stw $dst, sp[$b]",
-                 []>;
+                 (outs), (ins GRRegs:$val, i32imm:$index),
+                 "stw $val, sp[$index]",
+                 [(XCoreStwsp GRRegs:$val, immU6:$index)]>;
 
 def STWSP_lru6 : _FLRU6<
-                 (outs), (ins GRRegs:$dst, MEMii:$b),
-                 "stw $dst, sp[$b]",
-                 [(store GRRegs:$dst, ADDRspii:$b)]>;
-
-let mayStore=1 in
-def STWSP_ru6_2 : _FRU6<
-                 (outs), (ins GRRegs:$dst, i32imm:$b),
-                 "stw $dst, sp[$b]",
-                 []>;
-
-def STWSP_lru6_2 : _FLRU6<
-                 (outs), (ins GRRegs:$dst, i32imm:$b),
-                 "stw $dst, sp[$b]",
-                 [(store GRRegs:$dst, ADDRspii:$b)]>;
+                 (outs), (ins GRRegs:$val, i32imm:$index),
+                 "stw $val, sp[$index]",
+                 [(XCoreStwsp GRRegs:$val, immU16:$index)]>;
+}
 
-let mayLoad=1 in
+let mayLoad=1 in {
 def LDWSP_ru6 : _FRU6<
-                 (outs GRRegs:$dst), (ins MEMii:$b),
+                 (outs GRRegs:$dst), (ins i32imm:$b),
                  "ldw $dst, sp[$b]",
                  []>;
 
 def LDWSP_lru6 : _FLRU6<
-                 (outs GRRegs:$dst), (ins MEMii:$b),
+                 (outs GRRegs:$dst), (ins i32imm:$b),
                  "ldw $dst, sp[$b]",
-                 [(set GRRegs:$dst, (load ADDRspii:$b))]>;
+                 []>;
+}
 
-let neverHasSideEffects = 1 in
+let neverHasSideEffects = 1 in {
 def LDAWSP_ru6 : _FRU6<
-                 (outs GRRegs:$dst), (ins MEMii:$b),
+                 (outs GRRegs:$dst), (ins i32imm:$b),
                  "ldaw $dst, sp[$b]",
                  []>;
 
 def LDAWSP_lru6 : _FLRU6<
-                 (outs GRRegs:$dst), (ins MEMii:$b),
+                 (outs GRRegs:$dst), (ins i32imm:$b),
                  "ldaw $dst, sp[$b]",
-                 [(set GRRegs: $dst, ADDRspii:$b)]>;
+                 []>;
 
-let neverHasSideEffects = 1 in {
 def LDAWSP_ru6_RRegs : _FRU6<
                  (outs RRegs:$dst), (ins i32imm:$b),
                  "ldaw $dst, sp[$b]",
@@ -808,10 +824,6 @@ def GETID_0R : _F0R<(outs), (ins),
 
 def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BL_lu10 tglobaladdr:$addr)>;
 def : Pat<(XCoreBranchLink texternalsym:$addr), (BL_lu10 texternalsym:$addr)>;
-def : Pat<(XCoreStwsp GRRegs:$val, immU6:$index),
-          (STWSP_ru6_2 GRRegs:$val, immU6:$index)>;
-def : Pat<(XCoreStwsp GRRegs:$val, immU16:$index),
-          (STWSP_lru6_2 GRRegs:$val, immU16:$index)>;
 
 /// sext_inreg
 def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>;
@@ -823,7 +835,7 @@ def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)),
           (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
 def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
 
-def : Pat<(zextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
+def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
           (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
 def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
 
@@ -991,3 +1003,5 @@ def : Pat<(mul GRRegs:$src, -3),
 def : Pat<(sra GRRegs:$src, 31),
           (ASHR_l2rus GRRegs:$src, 32)>;
 
+def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm),
+          (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>;