if (!isU6 && !isImmU16(Amount)) {
// FIX could emit multiple instructions in this case.
#ifndef NDEBUG
- cerr << "eliminateCallFramePseudoInstr size too big: "
- << Amount << "\n";
+ errs() << "eliminateCallFramePseudoInstr size too big: "
+ << Amount << "\n";
#endif
- llvm_unreachable();
+ llvm_unreachable(0);
}
MachineInstr *New;
MBB.erase(I);
}
-void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
- int SPAdj, RegScavenger *RS) const {
+unsigned
+XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
+ int SPAdj, int *Value,
+ RegScavenger *RS) const {
assert(SPAdj == 0 && "Unexpected");
MachineInstr &MI = *II;
DebugLoc dl = MI.getDebugLoc();
int StackSize = MF.getFrameInfo()->getStackSize();
#ifndef NDEBUG
- DOUT << "\nFunction : " << MF.getFunction()->getName() << "\n";
- DOUT << "<--------->\n";
- MI.print(DOUT);
- DOUT << "FrameIndex : " << FrameIndex << "\n";
- DOUT << "FrameOffset : " << Offset << "\n";
- DOUT << "StackSize : " << StackSize << "\n";
+ DEBUG(errs() << "\nFunction : "
+ << MF.getFunction()->getName() << "\n");
+ DEBUG(errs() << "<--------->\n");
+ DEBUG(MI.print(errs()));
+ DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n");
+ DEBUG(errs() << "FrameOffset : " << Offset << "\n");
+ DEBUG(errs() << "StackSize : " << StackSize << "\n");
#endif
Offset += StackSize;
assert(Offset%4 == 0 && "Misaligned stack offset");
- #ifndef NDEBUG
- DOUT << "Offset : " << Offset << "\n";
- DOUT << "<--------->\n";
- #endif
+ DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
Offset/=4;
bool isUs = isImmUs(Offset);
unsigned FramePtr = XCore::R10;
- MachineInstr *New = 0;
if (!isUs) {
if (!RS) {
std::string msg;
loadConstant(MBB, II, ScratchReg, Offset, dl);
switch (MI.getOpcode()) {
case XCore::LDWFI:
- New = BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
+ BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
.addReg(FramePtr)
.addReg(ScratchReg, RegState::Kill);
break;
case XCore::STWFI:
- New = BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
+ BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
.addReg(Reg, getKillRegState(isKill))
.addReg(FramePtr)
.addReg(ScratchReg, RegState::Kill);
break;
case XCore::LDAWFI:
- New = BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
+ BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
.addReg(FramePtr)
.addReg(ScratchReg, RegState::Kill);
break;
default:
- LLVM_UNREACHABLE("Unexpected Opcode\n");
+ llvm_unreachable("Unexpected Opcode");
}
} else {
switch (MI.getOpcode()) {
case XCore::LDWFI:
- New = BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
+ BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
.addReg(FramePtr)
.addImm(Offset);
break;
case XCore::STWFI:
- New = BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
+ BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
.addReg(Reg, getKillRegState(isKill))
.addReg(FramePtr)
.addImm(Offset);
break;
case XCore::LDAWFI:
- New = BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
+ BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
.addReg(FramePtr)
.addImm(Offset);
break;
default:
- LLVM_UNREACHABLE("Unexpected Opcode\n");
+ llvm_unreachable("Unexpected Opcode");
}
}
} else {
.addImm(Offset);
break;
default:
- LLVM_UNREACHABLE("Unexpected Opcode\n");
+ llvm_unreachable("Unexpected Opcode");
}
}
// Erase old instruction.
MBB.erase(II);
+ return 0;
}
void