//
//===----------------------------------------------------------------------===//
-#include "XCoreTargetAsmInfo.h"
#include "XCoreTargetMachine.h"
+#include "XCoreTargetObjectFile.h"
+#include "XCoreTargetTransformInfo.h"
#include "XCore.h"
-#include "llvm/Module.h"
-#include "llvm/PassManager.h"
-#include "llvm/Target/TargetMachineRegistry.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/IR/Module.h"
+#include "llvm/IR/LegacyPassManager.h"
+#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
+/// XCoreTargetMachine ctor - Create an ILP32 architecture model
+///
+XCoreTargetMachine::XCoreTargetMachine(const Target &T, const Triple &TT,
+ StringRef CPU, StringRef FS,
+ const TargetOptions &Options,
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL)
+ : LLVMTargetMachine(
+ T, "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32",
+ TT, CPU, FS, Options, RM, CM, OL),
+ TLOF(make_unique<XCoreTargetObjectFile>()),
+ Subtarget(TT, CPU, FS, *this) {
+ initAsmInfo();
+}
+
+XCoreTargetMachine::~XCoreTargetMachine() {}
+
namespace {
- // Register the target.
- RegisterTarget<XCoreTargetMachine> X("xcore", " XCore");
+/// XCore Code Generator Pass Configuration Options.
+class XCorePassConfig : public TargetPassConfig {
+public:
+ XCorePassConfig(XCoreTargetMachine *TM, PassManagerBase &PM)
+ : TargetPassConfig(TM, PM) {}
+
+ XCoreTargetMachine &getXCoreTargetMachine() const {
+ return getTM<XCoreTargetMachine>();
+ }
+
+ void addIRPasses() override;
+ bool addPreISel() override;
+ bool addInstSelector() override;
+ void addPreEmitPass() override;
+};
+} // namespace
+
+TargetPassConfig *XCoreTargetMachine::createPassConfig(PassManagerBase &PM) {
+ return new XCorePassConfig(this, PM);
}
-const TargetAsmInfo *XCoreTargetMachine::createTargetAsmInfo() const {
- return new XCoreTargetAsmInfo(*this);
+void XCorePassConfig::addIRPasses() {
+ addPass(createAtomicExpandPass(&getXCoreTargetMachine()));
+
+ TargetPassConfig::addIRPasses();
}
-/// XCoreTargetMachine ctor - Create an ILP32 architecture model
-///
-XCoreTargetMachine::XCoreTargetMachine(const Module &M, const std::string &FS)
- : Subtarget(*this, M, FS),
- DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-"
- "i16:16:32-i32:32:32-i64:32:32"),
- InstrInfo(),
- FrameInfo(*this),
- TLInfo(*this) {
-}
-
-unsigned XCoreTargetMachine::getModuleMatchQuality(const Module &M) {
- std::string TT = M.getTargetTriple();
- if (TT.size() >= 6 && std::string(TT.begin(), TT.begin()+6) == "xcore-")
- return 20;
-
- // Otherwise we don't match.
- return 0;
-}
-
-bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
- PM.add(createXCoreISelDag(*this));
+bool XCorePassConfig::addPreISel() {
+ addPass(createXCoreLowerThreadLocalPass());
return false;
}
-bool XCoreTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast,
- raw_ostream &Out) {
- // Output assembly language.
- PM.add(createXCoreCodePrinterPass(Out, *this));
+bool XCorePassConfig::addInstSelector() {
+ addPass(createXCoreISelDag(getXCoreTargetMachine(), getOptLevel()));
return false;
}
+
+void XCorePassConfig::addPreEmitPass() {
+ addPass(createXCoreFrameToArgsOffsetEliminationPass(), false);
+}
+
+// Force static initialization.
+extern "C" void LLVMInitializeXCoreTarget() {
+ RegisterTargetMachine<XCoreTargetMachine> X(TheXCoreTarget);
+}
+
+TargetIRAnalysis XCoreTargetMachine::getTargetIRAnalysis() {
+ return TargetIRAnalysis([this](Function &F) {
+ return TargetTransformInfo(XCoreTTIImpl(this, F));
+ });
+}