#include "llvm/Function.h"
#include "llvm/Instructions.h"
#include "llvm/IntrinsicInst.h"
-#include "llvm/LLVMContext.h"
#include "llvm/Analysis/Dominators.h"
#include "llvm/Analysis/AliasSetTracker.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Support/CFG.h"
-#include "llvm/Support/Compiler.h"
#include <algorithm>
using namespace llvm;
static bool isEqual(const EltTy &LHS, const EltTy &RHS) {
return LHS == RHS;
}
- static bool isPod() { return true; }
};
}
return false; // Don't allow a store OF the AI, only INTO the AI.
if (SI->isVolatile())
return false;
- } else if (const BitCastInst *BC = dyn_cast<BitCastInst>(*UI)) {
- // A bitcast that does not feed into debug info inhibits promotion.
- if (!BC->hasOneUse() || !isa<DbgInfoIntrinsic>(*BC->use_begin()))
- return false;
- // If the only use is by debug info, this alloca will not exist in
- // non-debug code, so don't try to promote; this ensures the same
- // codegen with debug info. Otherwise, debug info should not
- // inhibit promotion (but we must examine other uses).
- if (AI->hasOneUse())
- return false;
} else {
return false;
}
public:
typedef std::vector<Value *> ValVector;
- RenamePassData() {}
+ RenamePassData() : BB(NULL), Pred(NULL), Values() {}
RenamePassData(BasicBlock *B, BasicBlock *P,
const ValVector &V) : BB(B), Pred(P), Values(V) {}
BasicBlock *BB;
///
AliasSetTracker *AST;
- LLVMContext &Context;
-
/// AllocaLookup - Reverse mapping of Allocas.
///
std::map<AllocaInst*, unsigned> AllocaLookup;
DenseMap<const BasicBlock*, unsigned> BBNumPreds;
public:
PromoteMem2Reg(const std::vector<AllocaInst*> &A, DominatorTree &dt,
- DominanceFrontier &df, AliasSetTracker *ast,
- LLVMContext &C)
- : Allocas(A), DT(dt), DF(df), AST(ast), Context(C) {}
+ DominanceFrontier &df, AliasSetTracker *ast)
+ : Allocas(A), DT(dt), DF(df), AST(ast) {}
void run();
for (Value::use_iterator UI = AI->use_begin(), E = AI->use_end();
UI != E;) {
Instruction *User = cast<Instruction>(*UI++);
- if (BitCastInst *BC = dyn_cast<BitCastInst>(User)) {
- // Remove any uses of this alloca in DbgInfoInstrinsics.
- assert(BC->hasOneUse() && "Unexpected alloca uses!");
- DbgInfoIntrinsic *DI = cast<DbgInfoIntrinsic>(*BC->use_begin());
- DI->eraseFromParent();
- BC->eraseFromParent();
- continue;
- }
-
+
if (StoreInst *SI = dyn_cast<StoreInst>(User)) {
// Remember the basic blocks which define new values for the alloca
DefiningBlocks.push_back(SI->getParent());
//
std::vector<RenamePassData> RenamePassWorkList;
RenamePassWorkList.push_back(RenamePassData(F.begin(), 0, Values));
- while (!RenamePassWorkList.empty()) {
+ do {
RenamePassData RPD;
RPD.swap(RenamePassWorkList.back());
RenamePassWorkList.pop_back();
// RenamePass may add new worklist entries.
RenamePass(RPD.BB, RPD.Pred, RPD.Values, RenamePassWorkList);
- }
+ } while (!RenamePassWorkList.empty());
// The renamer uses the Visited set to avoid infinite loops. Clear it now.
Visited.clear();
}
// Otherwise, we *can* safely rewrite this load.
- LI->replaceAllUsesWith(OnlyStore->getOperand(0));
+ Value *ReplVal = OnlyStore->getOperand(0);
+ // If the replacement value is the load, this must occur in unreachable
+ // code.
+ if (ReplVal == LI)
+ ReplVal = UndefValue::get(LI->getType());
+ LI->replaceAllUsesWith(ReplVal);
if (AST && isa<PointerType>(LI->getType()))
AST->deleteValue(LI);
LI->eraseFromParent();
///
void llvm::PromoteMemToReg(const std::vector<AllocaInst*> &Allocas,
DominatorTree &DT, DominanceFrontier &DF,
- LLVMContext &Context, AliasSetTracker *AST) {
+ AliasSetTracker *AST) {
// If there is nothing to do, bail out...
if (Allocas.empty()) return;
- PromoteMem2Reg(Allocas, DT, DF, AST, Context).run();
+ PromoteMem2Reg(Allocas, DT, DF, AST).run();
}