Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not in...

[oota-llvm.git] / lib / VMCore / Instruction.cpp

diff --git a/lib/VMCore/Instruction.cpp b/lib/VMCore/Instruction.cpp
index 9e55a083db0cc5f08cb839acd120e64f835836f7..73191c19658cc0e77d3f7ca53ef9fd856ec3ec33 100644 (file)
--- a/lib/VMCore/Instruction.cpp
+++ b/lib/VMCore/Instruction.cpp
@@ -320,7 +320,6 @@ bool Instruction::mayReadFromMemory() const {
   case Instruction::Fence: // FIXME: refine definition of mayReadFromMemory
   case Instruction::AtomicCmpXchg:
   case Instruction::AtomicRMW:
-  case Instruction::LandingPad:
     return true;
   case Instruction::Call:
     return !cast<CallInst>(this)->doesNotAccessMemory();
@@ -341,7 +340,6 @@ bool Instruction::mayWriteToMemory() const {
   case Instruction::VAArg:
   case Instruction::AtomicCmpXchg:
   case Instruction::AtomicRMW:
-  case Instruction::LandingPad:
     return true;
   case Instruction::Call:
     return !cast<CallInst>(this)->onlyReadsMemory();
@@ -357,7 +355,7 @@ bool Instruction::mayWriteToMemory() const {
 bool Instruction::mayThrow() const {
   if (const CallInst *CI = dyn_cast<CallInst>(this))
     return !CI->doesNotThrow();
-  return false;
+  return isa<ResumeInst>(this);
 }
 
 /// isAssociative - Return true if the instruction is associative:
@@ -438,6 +436,10 @@ bool Instruction::isSafeToSpeculativelyExecute() const {
   case Unwind:
   case Unreachable:
   case Fence:
+  case LandingPad:
+  case AtomicRMW:
+  case AtomicCmpXchg:
+  case Resume:
     return false; // Misc instructions which have effects
   }
 }