* published by the Free Software Foundation.
*/
-#ifndef __RT5640_H__
-#define __RT5640_H__
+#ifndef _RT5640_H
+#define _RT5640_H
+
+#include <linux/clk.h>
+#include <sound/rt5640.h>
/* Info */
#define RT5640_RESET 0x00
#define RT5640_SPK_VOL 0x01
#define RT5640_HP_VOL 0x02
#define RT5640_OUTPUT 0x03
-#define RT5640_MONO_OUT 0x04
-/* Dummy */
-#define RT5640_DUMMY_PR3F 0x05
+#define RT5640_MONO_OUT 0x04
/* I/O - Input */
#define RT5640_IN1_IN2 0x0d
#define RT5640_IN3_IN4 0x0e
#define RT5640_DAC2_DIG_VOL 0x1a
#define RT5640_DAC2_CTRL 0x1b
#define RT5640_ADC_DIG_VOL 0x1c
-#define RT5640_ADC_DATA 0x1d
+#define RT5640_ADC_DATA 0x1d
#define RT5640_ADC_BST_VOL 0x1e
/* Mixer - D-D */
#define RT5640_STO_ADC_MIXER 0x27
#define RT5640_OUT_R3_MIXER 0x52
#define RT5640_LOUT_MIXER 0x53
/* Power */
-#define RT5640_PWR_DIG1 0x61
-#define RT5640_PWR_DIG2 0x62
+#define RT5640_PWR_DIG1 0x61
+#define RT5640_PWR_DIG2 0x62
#define RT5640_PWR_ANLG1 0x63
#define RT5640_PWR_ANLG2 0x64
#define RT5640_PWR_MIXER 0x65
/* Format - ADC/DAC */
#define RT5640_I2S1_SDP 0x70
#define RT5640_I2S2_SDP 0x71
-#define RT5640_I2S3_SDP 0x72
#define RT5640_ADDA_CLK1 0x73
#define RT5640_ADDA_CLK2 0x74
#define RT5640_DMIC 0x75
#define RT5640_HP_OVCD 0x8b
#define RT5640_CLS_D_OVCD 0x8c
#define RT5640_CLS_D_OUT 0x8d
-#define RT5640_DEPOP_M1 0x8e
-#define RT5640_DEPOP_M2 0x8f
-#define RT5640_DEPOP_M3 0x90
+#define RT5640_DEPOP_M1 0x8e
+#define RT5640_DEPOP_M2 0x8f
+#define RT5640_DEPOP_M3 0x90
#define RT5640_CHARGE_PUMP 0x91
#define RT5640_PV_DET_SPK_G 0x92
#define RT5640_MICBIAS 0x93
#define RT5640_PGM_REG_ARR3 0xca
#define RT5640_PGM_REG_ARR4 0xcb
#define RT5640_PGM_REG_ARR5 0xcc
-#define RT5640_SCB_FUNC 0xcd
+#define RT5640_SCB_FUNC 0xcd
#define RT5640_SCB_CTRL 0xce
#define RT5640_BASE_BACK 0xcf
#define RT5640_MP3_PLUS1 0xd0
#define RT5640_MP3_PLUS2 0xd1
#define RT5640_3D_HP 0xd2
#define RT5640_ADJ_HPF 0xd3
-#define RT5640_HP_CALIB_AMP_DET 0xd6
+#define RT5640_HP_CALIB_AMP_DET 0xd6
#define RT5640_HP_CALIB2 0xd7
#define RT5640_SV_ZCD1 0xd9
#define RT5640_SV_ZCD2 0xda
-/* General Control */
-#define RT5640_GEN_CTRL1 0xfa
-#define RT5640_GEN_CTRL2 0xfb
-#define RT5640_GEN_CTRL3 0xfc
+/* Dummy Register */
+#define RT5640_DUMMY1 0xfa
+#define RT5640_DUMMY2 0xfb
+#define RT5640_DUMMY3 0xfc
/* Index of Codec Private Register definition */
-#define RT5640_BIAS_CUR1 0x12
-#define RT5640_BIAS_CUR3 0x14
-#define RT5640_CLSD_INT_REG1 0x1c
#define RT5640_CHPUMP_INT_REG1 0x24
#define RT5640_MAMP_INT_REG2 0x37
-#define RT5640_CHOP_DAC_ADC 0x3d
-#define RT5640_MIXER_INT_REG 0x3f
#define RT5640_3D_SPK 0x63
#define RT5640_WND_1 0x6c
#define RT5640_WND_2 0x6d
#define RT5640_EQ_GN_HIP2 0xb2
#define RT5640_EQ_PRE_VOL 0xb3
#define RT5640_EQ_PST_VOL 0xb4
-
+/* General Control */
+#define RT5640_GEN_CTRL1 0xfa
/* global definition */
#define RT5640_L_MUTE (0x1 << 15)
#define RT5640_R_VOL_MASK (0x3f)
#define RT5640_R_VOL_SFT 0
+/* SW Reset & Device ID (0x00) */
+#define RT5640_ID_MASK (0x3 << 1)
+#define RT5640_ID_5639 (0x0 << 1)
+#define RT5640_ID_5640 (0x2 << 1)
+#define RT5640_ID_5642 (0x3 << 1)
+
+
/* IN1 and IN2 Control (0x0d) */
/* IN3 and IN4 Control (0x0e) */
-#define RT5640_BST_MASK1 (0xf<<12)
#define RT5640_BST_SFT1 12
-#define RT5640_BST_MASK2 (0xf<<8)
#define RT5640_BST_SFT2 8
#define RT5640_IN_DF1 (0x1 << 7)
#define RT5640_IN_SFT1 7
#define RT5640_INR_VOL_SFT 0
/* DAC1 Digital Volume (0x19) */
-#define RT5640_DAC_L1_VOL_MASK (0xff << 8)
+#define RT5640_DAC_L1_VOL_MASK (0xff << 8)
#define RT5640_DAC_L1_VOL_SFT 8
-#define RT5640_DAC_R1_VOL_MASK (0xff)
+#define RT5640_DAC_R1_VOL_MASK (0xff)
#define RT5640_DAC_R1_VOL_SFT 0
/* DAC2 Digital Volume (0x1a) */
-#define RT5640_DAC_L2_VOL_MASK (0xff << 8)
+#define RT5640_DAC_L2_VOL_MASK (0xff << 8)
#define RT5640_DAC_L2_VOL_SFT 8
-#define RT5640_DAC_R2_VOL_MASK (0xff)
+#define RT5640_DAC_R2_VOL_MASK (0xff)
#define RT5640_DAC_R2_VOL_SFT 0
/* DAC2 Control (0x1b) */
#define RT5640_M_DAC_L2_VOL (0x1 << 13)
-#define RT5640_M_DAC_L2_VOL_SFT 13
+#define RT5640_M_DAC_L2_VOL_SFT 13
#define RT5640_M_DAC_R2_VOL (0x1 << 12)
-#define RT5640_M_DAC_R2_VOL_SFT 12
+#define RT5640_M_DAC_R2_VOL_SFT 12
/* ADC Digital Volume Control (0x1c) */
#define RT5640_ADC_L_VOL_MASK (0x7f << 8)
#define RT5640_ADC_COMP_SFT 10
/* Stereo ADC Mixer Control (0x27) */
-#define RT5640_M_ADC_L1 (0x1 << 14)
+#define RT5640_M_ADC_L1 (0x1 << 14)
#define RT5640_M_ADC_L1_SFT 14
-#define RT5640_M_ADC_L2 (0x1 << 13)
+#define RT5640_M_ADC_L2 (0x1 << 13)
#define RT5640_M_ADC_L2_SFT 13
#define RT5640_ADC_1_SRC_MASK (0x1 << 12)
#define RT5640_ADC_1_SRC_SFT 12
#define RT5640_ADC_1_SRC_ADC (0x1 << 12)
-#define RT5640_ADC_1_SRC_DACMIX (0x0 << 12)
+#define RT5640_ADC_1_SRC_DACMIX (0x0 << 12)
#define RT5640_ADC_2_SRC_MASK (0x3 << 10)
#define RT5640_ADC_2_SRC_SFT 10
-#define RT5640_ADC_2_SRC_DMIC1 (0x0 << 10)
-#define RT5640_ADC_2_SRC_DMIC2 (0x1 << 10)
-#define RT5640_ADC_2_SRC_DACMIX (0x2 << 10)
-#define RT5640_M_ADC_R1 (0x1 << 6)
+#define RT5640_ADC_2_SRC_DMIC1 (0x0 << 10)
+#define RT5640_ADC_2_SRC_DMIC2 (0x1 << 10)
+#define RT5640_ADC_2_SRC_DACMIX (0x2 << 10)
+#define RT5640_M_ADC_R1 (0x1 << 6)
#define RT5640_M_ADC_R1_SFT 6
-#define RT5640_M_ADC_R2 (0x1 << 5)
+#define RT5640_M_ADC_R2 (0x1 << 5)
#define RT5640_M_ADC_R2_SFT 5
/* Mono ADC Mixer Control (0x28) */
#define RT5640_M_MONO_ADC_L2_SFT 13
#define RT5640_MONO_ADC_L1_SRC_MASK (0x1 << 12)
#define RT5640_MONO_ADC_L1_SRC_SFT 12
-#define RT5640_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
+#define RT5640_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
#define RT5640_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
#define RT5640_MONO_ADC_L2_SRC_MASK (0x3 << 10)
#define RT5640_MONO_ADC_L2_SRC_SFT 10
-#define RT5640_MONO_ADC_L2_SRC_DMIC_L1 (0x0 << 10)
-#define RT5640_MONO_ADC_L2_SRC_DMIC_L2 (0x1 << 10)
-#define RT5640_MONO_ADC_L2_SRC_DACMIXL (0x2 << 10)
+#define RT5640_MONO_ADC_L2_SRC_DMIC_L1 (0x0 << 10)
+#define RT5640_MONO_ADC_L2_SRC_DMIC_L2 (0x1 << 10)
+#define RT5640_MONO_ADC_L2_SRC_DACMIXL (0x2 << 10)
#define RT5640_M_MONO_ADC_R1 (0x1 << 6)
#define RT5640_M_MONO_ADC_R1_SFT 6
#define RT5640_M_MONO_ADC_R2 (0x1 << 5)
#define RT5640_MONO_ADC_R1_SRC_MASK (0x1 << 4)
#define RT5640_MONO_ADC_R1_SRC_SFT 4
#define RT5640_MONO_ADC_R1_SRC_ADCR (0x1 << 4)
-#define RT5640_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4)
+#define RT5640_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4)
#define RT5640_MONO_ADC_R2_SRC_MASK (0x3 << 2)
#define RT5640_MONO_ADC_R2_SRC_SFT 2
-#define RT5640_MONO_ADC_R2_SRC_DMIC_R1 (0x0 << 2)
-#define RT5640_MONO_ADC_R2_SRC_DMIC_R2 (0x1 << 2)
-#define RT5640_MONO_ADC_R2_SRC_DACMIXR (0x2 << 2)
+#define RT5640_MONO_ADC_R2_SRC_DMIC_R1 (0x0 << 2)
+#define RT5640_MONO_ADC_R2_SRC_DMIC_R2 (0x1 << 2)
+#define RT5640_MONO_ADC_R2_SRC_DACMIXR (0x2 << 2)
/* ADC Mixer to DAC Mixer Control (0x29) */
#define RT5640_M_ADCMIX_L (0x1 << 15)
#define RT5640_M_IF1_DAC_R_SFT 6
/* Stereo DAC Mixer Control (0x2a) */
-#define RT5640_M_DAC_L1 (0x1 << 14)
+#define RT5640_M_DAC_L1 (0x1 << 14)
#define RT5640_M_DAC_L1_SFT 14
#define RT5640_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
#define RT5640_DAC_L1_STO_L_VOL_SFT 13
-#define RT5640_M_DAC_L2 (0x1 << 12)
+#define RT5640_M_DAC_L2 (0x1 << 12)
#define RT5640_M_DAC_L2_SFT 12
#define RT5640_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
#define RT5640_DAC_L2_STO_L_VOL_SFT 11
#define RT5640_M_ANC_DAC_L (0x1 << 10)
-#define RT5640_M_ANC_DAC_L_SFT 10
-#define RT5640_M_DAC_R1 (0x1 << 6)
+#define RT5640_M_ANC_DAC_L_SFT 10
+#define RT5640_M_DAC_R1 (0x1 << 6)
#define RT5640_M_DAC_R1_SFT 6
#define RT5640_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
#define RT5640_DAC_R1_STO_R_VOL_SFT 5
-#define RT5640_M_DAC_R2 (0x1 << 4)
+#define RT5640_M_DAC_R2 (0x1 << 4)
#define RT5640_M_DAC_R2_SFT 4
#define RT5640_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
#define RT5640_DAC_R2_STO_R_VOL_SFT 3
#define RT5640_M_ANC_DAC_R_SFT 2
/* Mono DAC Mixer Control (0x2b) */
-#define RT5640_M_DAC_L1_MONO_L (0x1 << 14)
+#define RT5640_M_DAC_L1_MONO_L (0x1 << 14)
#define RT5640_M_DAC_L1_MONO_L_SFT 14
-#define RT5640_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
+#define RT5640_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
#define RT5640_DAC_L1_MONO_L_VOL_SFT 13
-#define RT5640_M_DAC_L2_MONO_L (0x1 << 12)
+#define RT5640_M_DAC_L2_MONO_L (0x1 << 12)
#define RT5640_M_DAC_L2_MONO_L_SFT 12
-#define RT5640_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
+#define RT5640_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
#define RT5640_DAC_L2_MONO_L_VOL_SFT 11
-#define RT5640_M_DAC_R2_MONO_L (0x1 << 10)
+#define RT5640_M_DAC_R2_MONO_L (0x1 << 10)
#define RT5640_M_DAC_R2_MONO_L_SFT 10
-#define RT5640_DAC_R2_MONO_L_VOL_MASK (0x1 << 9)
+#define RT5640_DAC_R2_MONO_L_VOL_MASK (0x1 << 9)
#define RT5640_DAC_R2_MONO_L_VOL_SFT 9
-#define RT5640_M_DAC_R1_MONO_R (0x1 << 6)
+#define RT5640_M_DAC_R1_MONO_R (0x1 << 6)
#define RT5640_M_DAC_R1_MONO_R_SFT 6
-#define RT5640_DAC_R1_MONO_R_VOL_MASK (0x1 << 5)
+#define RT5640_DAC_R1_MONO_R_VOL_MASK (0x1 << 5)
#define RT5640_DAC_R1_MONO_R_VOL_SFT 5
-#define RT5640_M_DAC_R2_MONO_R (0x1 << 4)
+#define RT5640_M_DAC_R2_MONO_R (0x1 << 4)
#define RT5640_M_DAC_R2_MONO_R_SFT 4
-#define RT5640_DAC_R2_MONO_R_VOL_MASK (0x1 << 3)
+#define RT5640_DAC_R2_MONO_R_VOL_MASK (0x1 << 3)
#define RT5640_DAC_R2_MONO_R_VOL_SFT 3
-#define RT5640_M_DAC_L2_MONO_R (0x1 << 2)
+#define RT5640_M_DAC_L2_MONO_R (0x1 << 2)
#define RT5640_M_DAC_L2_MONO_R_SFT 2
-#define RT5640_DAC_L2_MONO_R_VOL_MASK (0x1 << 1)
+#define RT5640_DAC_L2_MONO_R_VOL_MASK (0x1 << 1)
#define RT5640_DAC_L2_MONO_R_VOL_SFT 1
/* Digital Mixer Control (0x2c) */
#define RT5640_TXDP_SRC_DIV3 (0x1 << 14)
/* DSP Path Control 2 (0x2e) */
-#define RT5640_DAC_L2_SEL_MASK (0x3 << 14)
+#define RT5640_DAC_L2_SEL_MASK (0x3 << 14)
#define RT5640_DAC_L2_SEL_SFT 14
#define RT5640_DAC_L2_SEL_IF2 (0x0 << 14)
#define RT5640_DAC_L2_SEL_IF3 (0x1 << 14)
#define RT5640_DAC_L2_SEL_TXDC (0x2 << 14)
#define RT5640_DAC_L2_SEL_BASS (0x3 << 14)
-#define RT5640_DAC_R2_SEL_MASK (0x3 << 12)
+#define RT5640_DAC_R2_SEL_MASK (0x3 << 12)
#define RT5640_DAC_R2_SEL_SFT 12
#define RT5640_DAC_R2_SEL_IF2 (0x0 << 12)
#define RT5640_DAC_R2_SEL_IF3 (0x1 << 12)
-#define RT5640_DAC_R2_SEL_TXDC (0x2 << 12)
+#define RT5640_DAC_R2_SEL_TXDC (0x2 << 12)
#define RT5640_IF2_ADC_L_SEL_MASK (0x1 << 11)
#define RT5640_IF2_ADC_L_SEL_SFT 11
#define RT5640_IF2_ADC_L_SEL_TXDP (0x0 << 11)
#define RT5640_TRXDP_SEL_SWAP (0x3 << 2)
/* Digital Interface Data Control (0x2f) */
-#define RT5640_IF1_DAC_SEL_MASK (0x3 << 14)
+#define RT5640_IF1_DAC_SEL_MASK (0x3 << 14)
#define RT5640_IF1_DAC_SEL_SFT 14
#define RT5640_IF1_DAC_SEL_NOR (0x0 << 14)
-#define RT5640_IF1_DAC_SEL_L2R (0x1 << 14)
-#define RT5640_IF1_DAC_SEL_R2L (0x2 << 14)
-#define RT5640_IF1_DAC_SEL_SWAP (0x3 << 14)
-#define RT5640_IF1_ADC_SEL_MASK (0x3 << 12)
+#define RT5640_IF1_DAC_SEL_SWAP (0x1 << 14)
+#define RT5640_IF1_DAC_SEL_L2R (0x2 << 14)
+#define RT5640_IF1_DAC_SEL_R2L (0x3 << 14)
+#define RT5640_IF1_ADC_SEL_MASK (0x3 << 12)
#define RT5640_IF1_ADC_SEL_SFT 12
#define RT5640_IF1_ADC_SEL_NOR (0x0 << 12)
-#define RT5640_IF1_ADC_SEL_L2R (0x1 << 12)
-#define RT5640_IF1_ADC_SEL_R2L (0x2 << 12)
-#define RT5640_IF1_ADC_SEL_SWAP (0x3 << 12)
-#define RT5640_IF2_DAC_SEL_MASK (0x3 << 10)
+#define RT5640_IF1_ADC_SEL_SWAP (0x1 << 12)
+#define RT5640_IF1_ADC_SEL_L2R (0x2 << 12)
+#define RT5640_IF1_ADC_SEL_R2L (0x3 << 12)
+#define RT5640_IF2_DAC_SEL_MASK (0x3 << 10)
#define RT5640_IF2_DAC_SEL_SFT 10
#define RT5640_IF2_DAC_SEL_NOR (0x0 << 10)
-#define RT5640_IF2_DAC_SEL_L2R (0x1 << 10)
-#define RT5640_IF2_DAC_SEL_R2L (0x2 << 10)
-#define RT5640_IF2_DAC_SEL_SWAP (0x3 << 10)
-#define RT5640_IF2_ADC_SEL_MASK (0x3 << 8)
+#define RT5640_IF2_DAC_SEL_SWAP (0x1 << 10)
+#define RT5640_IF2_DAC_SEL_L2R (0x2 << 10)
+#define RT5640_IF2_DAC_SEL_R2L (0x3 << 10)
+#define RT5640_IF2_ADC_SEL_MASK (0x3 << 8)
#define RT5640_IF2_ADC_SEL_SFT 8
#define RT5640_IF2_ADC_SEL_NOR (0x0 << 8)
-#define RT5640_IF2_ADC_SEL_L2R (0x1 << 8)
-#define RT5640_IF2_ADC_SEL_R2L (0x2 << 8)
-#define RT5640_IF2_ADC_SEL_SWAP (0x3 << 8)
-#define RT5640_IF3_DAC_SEL_MASK (0x3 << 6)
+#define RT5640_IF2_ADC_SEL_SWAP (0x1 << 8)
+#define RT5640_IF2_ADC_SEL_L2R (0x2 << 8)
+#define RT5640_IF2_ADC_SEL_R2L (0x3 << 8)
+#define RT5640_IF3_DAC_SEL_MASK (0x3 << 6)
#define RT5640_IF3_DAC_SEL_SFT 6
#define RT5640_IF3_DAC_SEL_NOR (0x0 << 6)
-#define RT5640_IF3_DAC_SEL_L2R (0x1 << 6)
-#define RT5640_IF3_DAC_SEL_R2L (0x2 << 6)
-#define RT5640_IF3_DAC_SEL_SWAP (0x3 << 6)
-#define RT5640_IF3_ADC_SEL_MASK (0x3 << 4)
+#define RT5640_IF3_DAC_SEL_SWAP (0x1 << 6)
+#define RT5640_IF3_DAC_SEL_L2R (0x2 << 6)
+#define RT5640_IF3_DAC_SEL_R2L (0x3 << 6)
+#define RT5640_IF3_ADC_SEL_MASK (0x3 << 4)
#define RT5640_IF3_ADC_SEL_SFT 4
#define RT5640_IF3_ADC_SEL_NOR (0x0 << 4)
-#define RT5640_IF3_ADC_SEL_L2R (0x1 << 4)
-#define RT5640_IF3_ADC_SEL_R2L (0x2 << 4)
-#define RT5640_IF3_ADC_SEL_SWAP (0x3 << 4)
+#define RT5640_IF3_ADC_SEL_SWAP (0x1 << 4)
+#define RT5640_IF3_ADC_SEL_L2R (0x2 << 4)
+#define RT5640_IF3_ADC_SEL_R2L (0x3 << 4)
/* REC Left Mixer Control 1 (0x3b) */
-#define RT5640_G_HP_L_RM_L_MASK (0x7 << 13)
+#define RT5640_G_HP_L_RM_L_MASK (0x7 << 13)
#define RT5640_G_HP_L_RM_L_SFT 13
-#define RT5640_G_IN_L_RM_L_MASK (0x7 << 10)
+#define RT5640_G_IN_L_RM_L_MASK (0x7 << 10)
#define RT5640_G_IN_L_RM_L_SFT 10
-#define RT5640_G_BST4_RM_L_MASK (0x7 << 7)
+#define RT5640_G_BST4_RM_L_MASK (0x7 << 7)
#define RT5640_G_BST4_RM_L_SFT 7
-#define RT5640_G_BST3_RM_L_MASK (0x7 << 4)
+#define RT5640_G_BST3_RM_L_MASK (0x7 << 4)
#define RT5640_G_BST3_RM_L_SFT 4
-#define RT5640_G_BST2_RM_L_MASK (0x7 << 1)
+#define RT5640_G_BST2_RM_L_MASK (0x7 << 1)
#define RT5640_G_BST2_RM_L_SFT 1
/* REC Left Mixer Control 2 (0x3c) */
-#define RT5640_G_BST1_RM_L_MASK (0x7 << 13)
+#define RT5640_G_BST1_RM_L_MASK (0x7 << 13)
#define RT5640_G_BST1_RM_L_SFT 13
-#define RT5640_G_OM_L_RM_L_MASK (0x7 << 10)
-#define RT5640_G_OM_L_RM_L_SFT 10
+#define RT5640_G_OM_L_RM_L_MASK (0x7 << 10)
+#define RT5640_G_OM_L_RM_L_SFT 10
#define RT5640_M_HP_L_RM_L (0x1 << 6)
-#define RT5640_M_HP_L_RM_L_SFT 6
+#define RT5640_M_HP_L_RM_L_SFT 6
#define RT5640_M_IN_L_RM_L (0x1 << 5)
#define RT5640_M_IN_L_RM_L_SFT 5
#define RT5640_M_BST4_RM_L (0x1 << 4)
-#define RT5640_M_BST4_RM_L_SFT 4
+#define RT5640_M_BST4_RM_L_SFT 4
#define RT5640_M_BST3_RM_L (0x1 << 3)
-#define RT5640_M_BST3_RM_L_SFT 3
+#define RT5640_M_BST3_RM_L_SFT 3
#define RT5640_M_BST2_RM_L (0x1 << 2)
-#define RT5640_M_BST2_RM_L_SFT 2
+#define RT5640_M_BST2_RM_L_SFT 2
#define RT5640_M_BST1_RM_L (0x1 << 1)
-#define RT5640_M_BST1_RM_L_SFT 1
+#define RT5640_M_BST1_RM_L_SFT 1
#define RT5640_M_OM_L_RM_L (0x1)
-#define RT5640_M_OM_L_RM_L_SFT 0
+#define RT5640_M_OM_L_RM_L_SFT 0
/* REC Right Mixer Control 1 (0x3d) */
-#define RT5640_G_HP_R_RM_R_MASK (0x7 << 13)
-#define RT5640_G_HP_R_RM_R_SFT 13
-#define RT5640_G_IN_R_RM_R_MASK (0x7 << 10)
+#define RT5640_G_HP_R_RM_R_MASK (0x7 << 13)
+#define RT5640_G_HP_R_RM_R_SFT 13
+#define RT5640_G_IN_R_RM_R_MASK (0x7 << 10)
#define RT5640_G_IN_R_RM_R_SFT 10
-#define RT5640_G_BST4_RM_R_MASK (0x7 << 7)
+#define RT5640_G_BST4_RM_R_MASK (0x7 << 7)
#define RT5640_G_BST4_RM_R_SFT 7
-#define RT5640_G_BST3_RM_R_MASK (0x7 << 4)
+#define RT5640_G_BST3_RM_R_MASK (0x7 << 4)
#define RT5640_G_BST3_RM_R_SFT 4
-#define RT5640_G_BST2_RM_R_MASK (0x7 << 1)
+#define RT5640_G_BST2_RM_R_MASK (0x7 << 1)
#define RT5640_G_BST2_RM_R_SFT 1
/* REC Right Mixer Control 2 (0x3e) */
-#define RT5640_G_BST1_RM_R_MASK (0x7 << 13)
+#define RT5640_G_BST1_RM_R_MASK (0x7 << 13)
#define RT5640_G_BST1_RM_R_SFT 13
-#define RT5640_G_OM_R_RM_R_MASK (0x7 << 10)
-#define RT5640_G_OM_R_RM_R_SFT 10
+#define RT5640_G_OM_R_RM_R_MASK (0x7 << 10)
+#define RT5640_G_OM_R_RM_R_SFT 10
#define RT5640_M_HP_R_RM_R (0x1 << 6)
-#define RT5640_M_HP_R_RM_R_SFT 6
+#define RT5640_M_HP_R_RM_R_SFT 6
#define RT5640_M_IN_R_RM_R (0x1 << 5)
#define RT5640_M_IN_R_RM_R_SFT 5
#define RT5640_M_BST4_RM_R (0x1 << 4)
-#define RT5640_M_BST4_RM_R_SFT 4
+#define RT5640_M_BST4_RM_R_SFT 4
#define RT5640_M_BST3_RM_R (0x1 << 3)
-#define RT5640_M_BST3_RM_R_SFT 3
+#define RT5640_M_BST3_RM_R_SFT 3
#define RT5640_M_BST2_RM_R (0x1 << 2)
-#define RT5640_M_BST2_RM_R_SFT 2
+#define RT5640_M_BST2_RM_R_SFT 2
#define RT5640_M_BST1_RM_R (0x1 << 1)
-#define RT5640_M_BST1_RM_R_SFT 1
+#define RT5640_M_BST1_RM_R_SFT 1
#define RT5640_M_OM_R_RM_R (0x1)
-#define RT5640_M_OM_R_RM_R_SFT 0
+#define RT5640_M_OM_R_RM_R_SFT 0
/* HPMIX Control (0x45) */
#define RT5640_M_DAC2_HM (0x1 << 15)
#define RT5640_G_HPOMIX_SFT 12
/* SPK Left Mixer Control (0x46) */
-#define RT5640_G_RM_L_SM_L_MASK (0x3 << 14)
-#define RT5640_G_RM_L_SM_L_SFT 14
-#define RT5640_G_IN_L_SM_L_MASK (0x3 << 12)
+#define RT5640_G_RM_L_SM_L_MASK (0x3 << 14)
+#define RT5640_G_RM_L_SM_L_SFT 14
+#define RT5640_G_IN_L_SM_L_MASK (0x3 << 12)
#define RT5640_G_IN_L_SM_L_SFT 12
#define RT5640_G_DAC_L1_SM_L_MASK (0x3 << 10)
#define RT5640_G_DAC_L1_SM_L_SFT 10
#define RT5640_G_DAC_L2_SM_L_MASK (0x3 << 8)
#define RT5640_G_DAC_L2_SM_L_SFT 8
-#define RT5640_G_OM_L_SM_L_MASK (0x3 << 6)
-#define RT5640_G_OM_L_SM_L_SFT 6
+#define RT5640_G_OM_L_SM_L_MASK (0x3 << 6)
+#define RT5640_G_OM_L_SM_L_SFT 6
#define RT5640_M_RM_L_SM_L (0x1 << 5)
-#define RT5640_M_RM_L_SM_L_SFT 5
+#define RT5640_M_RM_L_SM_L_SFT 5
#define RT5640_M_IN_L_SM_L (0x1 << 4)
#define RT5640_M_IN_L_SM_L_SFT 4
#define RT5640_M_DAC_L1_SM_L (0x1 << 3)
#define RT5640_M_OM_L_SM_L_SFT 1
/* SPK Right Mixer Control (0x47) */
-#define RT5640_G_RM_R_SM_R_MASK (0x3 << 14)
-#define RT5640_G_RM_R_SM_R_SFT 14
-#define RT5640_G_IN_R_SM_R_MASK (0x3 << 12)
+#define RT5640_G_RM_R_SM_R_MASK (0x3 << 14)
+#define RT5640_G_RM_R_SM_R_SFT 14
+#define RT5640_G_IN_R_SM_R_MASK (0x3 << 12)
#define RT5640_G_IN_R_SM_R_SFT 12
#define RT5640_G_DAC_R1_SM_R_MASK (0x3 << 10)
#define RT5640_G_DAC_R1_SM_R_SFT 10
#define RT5640_G_DAC_R2_SM_R_MASK (0x3 << 8)
#define RT5640_G_DAC_R2_SM_R_SFT 8
-#define RT5640_G_OM_R_SM_R_MASK (0x3 << 6)
-#define RT5640_G_OM_R_SM_R_SFT 6
+#define RT5640_G_OM_R_SM_R_MASK (0x3 << 6)
+#define RT5640_G_OM_R_SM_R_SFT 6
#define RT5640_M_RM_R_SM_R (0x1 << 5)
-#define RT5640_M_RM_R_SM_R_SFT 5
+#define RT5640_M_RM_R_SM_R_SFT 5
#define RT5640_M_IN_R_SM_R (0x1 << 4)
#define RT5640_M_IN_R_SM_R_SFT 4
#define RT5640_M_DAC_R1_SM_R (0x1 << 3)
#define RT5640_M_DAC_R2_SM_R (0x1 << 2)
#define RT5640_M_DAC_R2_SM_R_SFT 2
#define RT5640_M_OM_R_SM_R (0x1 << 1)
-#define RT5640_M_OM_R_SM_R_SFT 1
+#define RT5640_M_OM_R_SM_R_SFT 1
/* SPOLMIX Control (0x48) */
#define RT5640_M_DAC_R1_SPM_L (0x1 << 15)
#define RT5640_M_DAC_L1_SPM_L (0x1 << 14)
#define RT5640_M_DAC_L1_SPM_L_SFT 14
#define RT5640_M_SV_R_SPM_L (0x1 << 13)
-#define RT5640_M_SV_R_SPM_L_SFT 13
+#define RT5640_M_SV_R_SPM_L_SFT 13
#define RT5640_M_SV_L_SPM_L (0x1 << 12)
-#define RT5640_M_SV_L_SPM_L_SFT 12
+#define RT5640_M_SV_L_SPM_L_SFT 12
#define RT5640_M_BST1_SPM_L (0x1 << 11)
-#define RT5640_M_BST1_SPM_L_SFT 11
+#define RT5640_M_BST1_SPM_L_SFT 11
/* SPORMIX Control (0x49) */
#define RT5640_M_DAC_R1_SPM_R (0x1 << 13)
#define RT5640_M_DAC_R1_SPM_R_SFT 13
#define RT5640_M_SV_R_SPM_R (0x1 << 12)
-#define RT5640_M_SV_R_SPM_R_SFT 12
+#define RT5640_M_SV_R_SPM_R_SFT 12
#define RT5640_M_BST1_SPM_R (0x1 << 11)
-#define RT5640_M_BST1_SPM_R_SFT 11
+#define RT5640_M_BST1_SPM_R_SFT 11
/* SPOLMIX / SPORMIX Ratio Control (0x4a) */
#define RT5640_SPO_CLSD_RATIO_MASK (0x7)
/* Mono Output Mixer Control (0x4c) */
#define RT5640_M_DAC_R2_MM (0x1 << 15)
-#define RT5640_M_DAC_R2_MM_SFT 15
+#define RT5640_M_DAC_R2_MM_SFT 15
#define RT5640_M_DAC_L2_MM (0x1 << 14)
-#define RT5640_M_DAC_L2_MM_SFT 14
+#define RT5640_M_DAC_L2_MM_SFT 14
#define RT5640_M_OV_R_MM (0x1 << 13)
#define RT5640_M_OV_R_MM_SFT 13
#define RT5640_M_OV_L_MM (0x1 << 12)
#define RT5640_M_OV_L_MM_SFT 12
#define RT5640_M_BST1_MM (0x1 << 11)
#define RT5640_M_BST1_MM_SFT 11
-#define RT5640_G_MONOMIX_MASK (0x1 << 10)
+#define RT5640_G_MONOMIX_MASK (0x1 << 10)
#define RT5640_G_MONOMIX_SFT 10
/* Output Left Mixer Control 1 (0x4d) */
-#define RT5640_G_BST3_OM_L_MASK (0x7 << 13)
-#define RT5640_G_BST3_OM_L_SFT 13
-#define RT5640_G_BST2_OM_L_MASK (0x7 << 10)
-#define RT5640_G_BST2_OM_L_SFT 10
-#define RT5640_G_BST1_OM_L_MASK (0x7 << 7)
-#define RT5640_G_BST1_OM_L_SFT 7
-#define RT5640_G_IN_L_OM_L_MASK (0x7 << 4)
+#define RT5640_G_BST3_OM_L_MASK (0x7 << 13)
+#define RT5640_G_BST3_OM_L_SFT 13
+#define RT5640_G_BST2_OM_L_MASK (0x7 << 10)
+#define RT5640_G_BST2_OM_L_SFT 10
+#define RT5640_G_BST1_OM_L_MASK (0x7 << 7)
+#define RT5640_G_BST1_OM_L_SFT 7
+#define RT5640_G_IN_L_OM_L_MASK (0x7 << 4)
#define RT5640_G_IN_L_OM_L_SFT 4
-#define RT5640_G_RM_L_OM_L_MASK (0x7 << 1)
-#define RT5640_G_RM_L_OM_L_SFT 1
+#define RT5640_G_RM_L_OM_L_MASK (0x7 << 1)
+#define RT5640_G_RM_L_OM_L_SFT 1
/* Output Left Mixer Control 2 (0x4e) */
#define RT5640_G_DAC_R2_OM_L_MASK (0x7 << 13)
/* Output Left Mixer Control 3 (0x4f) */
#define RT5640_M_SM_L_OM_L (0x1 << 8)
-#define RT5640_M_SM_L_OM_L_SFT 8
+#define RT5640_M_SM_L_OM_L_SFT 8
#define RT5640_M_BST3_OM_L (0x1 << 7)
-#define RT5640_M_BST3_OM_L_SFT 7
+#define RT5640_M_BST3_OM_L_SFT 7
#define RT5640_M_BST2_OM_L (0x1 << 6)
-#define RT5640_M_BST2_OM_L_SFT 6
+#define RT5640_M_BST2_OM_L_SFT 6
#define RT5640_M_BST1_OM_L (0x1 << 5)
-#define RT5640_M_BST1_OM_L_SFT 5
+#define RT5640_M_BST1_OM_L_SFT 5
#define RT5640_M_IN_L_OM_L (0x1 << 4)
#define RT5640_M_IN_L_OM_L_SFT 4
#define RT5640_M_RM_L_OM_L (0x1 << 3)
-#define RT5640_M_RM_L_OM_L_SFT 3
+#define RT5640_M_RM_L_OM_L_SFT 3
#define RT5640_M_DAC_R2_OM_L (0x1 << 2)
#define RT5640_M_DAC_R2_OM_L_SFT 2
#define RT5640_M_DAC_L2_OM_L (0x1 << 1)
#define RT5640_M_DAC_L1_OM_L_SFT 0
/* Output Right Mixer Control 1 (0x50) */
-#define RT5640_G_BST4_OM_R_MASK (0x7 << 13)
-#define RT5640_G_BST4_OM_R_SFT 13
-#define RT5640_G_BST2_OM_R_MASK (0x7 << 10)
-#define RT5640_G_BST2_OM_R_SFT 10
-#define RT5640_G_BST1_OM_R_MASK (0x7 << 7)
-#define RT5640_G_BST1_OM_R_SFT 7
-#define RT5640_G_IN_R_OM_R_MASK (0x7 << 4)
+#define RT5640_G_BST4_OM_R_MASK (0x7 << 13)
+#define RT5640_G_BST4_OM_R_SFT 13
+#define RT5640_G_BST2_OM_R_MASK (0x7 << 10)
+#define RT5640_G_BST2_OM_R_SFT 10
+#define RT5640_G_BST1_OM_R_MASK (0x7 << 7)
+#define RT5640_G_BST1_OM_R_SFT 7
+#define RT5640_G_IN_R_OM_R_MASK (0x7 << 4)
#define RT5640_G_IN_R_OM_R_SFT 4
-#define RT5640_G_RM_R_OM_R_MASK (0x7 << 1)
-#define RT5640_G_RM_R_OM_R_SFT 1
+#define RT5640_G_RM_R_OM_R_MASK (0x7 << 1)
+#define RT5640_G_RM_R_OM_R_SFT 1
/* Output Right Mixer Control 2 (0x51) */
#define RT5640_G_DAC_L2_OM_R_MASK (0x7 << 13)
/* Output Right Mixer Control 3 (0x52) */
#define RT5640_M_SM_L_OM_R (0x1 << 8)
-#define RT5640_M_SM_L_OM_R_SFT 8
+#define RT5640_M_SM_L_OM_R_SFT 8
#define RT5640_M_BST4_OM_R (0x1 << 7)
-#define RT5640_M_BST4_OM_R_SFT 7
+#define RT5640_M_BST4_OM_R_SFT 7
#define RT5640_M_BST2_OM_R (0x1 << 6)
-#define RT5640_M_BST2_OM_R_SFT 6
+#define RT5640_M_BST2_OM_R_SFT 6
#define RT5640_M_BST1_OM_R (0x1 << 5)
-#define RT5640_M_BST1_OM_R_SFT 5
+#define RT5640_M_BST1_OM_R_SFT 5
#define RT5640_M_IN_R_OM_R (0x1 << 4)
-#define RT5640_M_IN_R_OM_R_SFT 4
+#define RT5640_M_IN_R_OM_R_SFT 4
#define RT5640_M_RM_R_OM_R (0x1 << 3)
-#define RT5640_M_RM_R_OM_R_SFT 3
+#define RT5640_M_RM_R_OM_R_SFT 3
#define RT5640_M_DAC_L2_OM_R (0x1 << 2)
#define RT5640_M_DAC_L2_OM_R_SFT 2
#define RT5640_M_DAC_R2_OM_R (0x1 << 1)
/* LOUT Mixer Control (0x53) */
#define RT5640_M_DAC_L1_LM (0x1 << 15)
-#define RT5640_M_DAC_L1_LM_SFT 15
+#define RT5640_M_DAC_L1_LM_SFT 15
#define RT5640_M_DAC_R1_LM (0x1 << 14)
-#define RT5640_M_DAC_R1_LM_SFT 14
+#define RT5640_M_DAC_R1_LM_SFT 14
#define RT5640_M_OV_L_LM (0x1 << 13)
#define RT5640_M_OV_L_LM_SFT 13
#define RT5640_M_OV_R_LM (0x1 << 12)
#define RT5640_PWR_I2S1_BIT 15
#define RT5640_PWR_I2S2 (0x1 << 14)
#define RT5640_PWR_I2S2_BIT 14
-#define RT5640_PWR_I2S3 (0x1 << 13)
-#define RT5640_PWR_I2S3_BIT 13
#define RT5640_PWR_DAC_L1 (0x1 << 12)
#define RT5640_PWR_DAC_L1_BIT 12
#define RT5640_PWR_DAC_R1 (0x1 << 11)
#define RT5640_PWR_ADC_SF (0x1 << 15)
#define RT5640_PWR_ADC_SF_BIT 15
#define RT5640_PWR_ADC_MF_L (0x1 << 14)
-#define RT5640_PWR_ADC_MF_L_BIT 14
+#define RT5640_PWR_ADC_MF_L_BIT 14
#define RT5640_PWR_ADC_MF_R (0x1 << 13)
-#define RT5640_PWR_ADC_MF_R_BIT 13
+#define RT5640_PWR_ADC_MF_R_BIT 13
#define RT5640_PWR_I2S_DSP (0x1 << 12)
#define RT5640_PWR_I2S_DSP_BIT 12
#define RT5640_PWR_MM_BIT 10
#define RT5640_PWR_MA (0x1 << 8)
#define RT5640_PWR_MA_BIT 8
-#define RT5640_PWR_HP_L (0x1 << 7)
+#define RT5640_PWR_HP_L (0x1 << 7)
#define RT5640_PWR_HP_L_BIT 7
-#define RT5640_PWR_HP_R (0x1 << 6)
+#define RT5640_PWR_HP_R (0x1 << 6)
#define RT5640_PWR_HP_R_BIT 6
#define RT5640_PWR_HA (0x1 << 5)
#define RT5640_PWR_HA_BIT 5
#define RT5640_PWR_VREF2_BIT 4
#define RT5640_PWR_FV2 (0x1 << 3)
#define RT5640_PWR_FV2_BIT 3
-#define RT5640_PWR_LDO2 (0x1 << 2)
+#define RT5640_PWR_LDO2 (0x1 << 2)
#define RT5640_PWR_LDO2_BIT 2
/* Power Management for Analog 2 (0x64) */
-#define RT5640_PWR_BST1 (0x1 << 15)
+#define RT5640_PWR_BST1 (0x1 << 15)
#define RT5640_PWR_BST1_BIT 15
-#define RT5640_PWR_BST2 (0x1 << 14)
+#define RT5640_PWR_BST2 (0x1 << 14)
#define RT5640_PWR_BST2_BIT 14
-#define RT5640_PWR_BST3 (0x1 << 13)
+#define RT5640_PWR_BST3 (0x1 << 13)
#define RT5640_PWR_BST3_BIT 13
-#define RT5640_PWR_BST4 (0x1 << 12)
+#define RT5640_PWR_BST4 (0x1 << 12)
#define RT5640_PWR_BST4_BIT 12
#define RT5640_PWR_MB1 (0x1 << 11)
#define RT5640_PWR_MB1_BIT 11
-#define RT5640_PWR_MB2 (0x1 << 10)
-#define RT5640_PWR_MB2_BIT 10
#define RT5640_PWR_PLL (0x1 << 9)
#define RT5640_PWR_PLL_BIT 9
/* Power Management for Mixer (0x65) */
-#define RT5640_PWR_OM_L (0x1 << 15)
+#define RT5640_PWR_OM_L (0x1 << 15)
#define RT5640_PWR_OM_L_BIT 15
-#define RT5640_PWR_OM_R (0x1 << 14)
+#define RT5640_PWR_OM_R (0x1 << 14)
#define RT5640_PWR_OM_R_BIT 14
-#define RT5640_PWR_SM_L (0x1 << 13)
+#define RT5640_PWR_SM_L (0x1 << 13)
#define RT5640_PWR_SM_L_BIT 13
-#define RT5640_PWR_SM_R (0x1 << 12)
+#define RT5640_PWR_SM_R (0x1 << 12)
#define RT5640_PWR_SM_R_BIT 12
-#define RT5640_PWR_RM_L (0x1 << 11)
+#define RT5640_PWR_RM_L (0x1 << 11)
#define RT5640_PWR_RM_L_BIT 11
-#define RT5640_PWR_RM_R (0x1 << 10)
+#define RT5640_PWR_RM_R (0x1 << 10)
#define RT5640_PWR_RM_R_BIT 10
/* Power Management for Volume (0x66) */
-#define RT5640_PWR_SV_L (0x1 << 15)
+#define RT5640_PWR_SV_L (0x1 << 15)
#define RT5640_PWR_SV_L_BIT 15
-#define RT5640_PWR_SV_R (0x1 << 14)
+#define RT5640_PWR_SV_R (0x1 << 14)
#define RT5640_PWR_SV_R_BIT 14
-#define RT5640_PWR_OV_L (0x1 << 13)
+#define RT5640_PWR_OV_L (0x1 << 13)
#define RT5640_PWR_OV_L_BIT 13
-#define RT5640_PWR_OV_R (0x1 << 12)
+#define RT5640_PWR_OV_R (0x1 << 12)
#define RT5640_PWR_OV_R_BIT 12
-#define RT5640_PWR_HV_L (0x1 << 11)
+#define RT5640_PWR_HV_L (0x1 << 11)
#define RT5640_PWR_HV_L_BIT 11
-#define RT5640_PWR_HV_R (0x1 << 10)
+#define RT5640_PWR_HV_R (0x1 << 10)
#define RT5640_PWR_HV_R_BIT 10
#define RT5640_PWR_IN_L (0x1 << 9)
#define RT5640_PWR_IN_L_BIT 9
-#define RT5640_PWR_IN_R (0x1 << 8)
+#define RT5640_PWR_IN_R (0x1 << 8)
#define RT5640_PWR_IN_R_BIT 8
/* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71 0x72) */
#define RT5640_I2S_MS_MASK (0x1 << 15)
#define RT5640_I2S_MS_SFT 15
-#define RT5640_I2S_MS_M (0x0 << 15)
+#define RT5640_I2S_MS_M (0x0 << 15)
#define RT5640_I2S_MS_S (0x1 << 15)
#define RT5640_I2S_IF_MASK (0x7 << 12)
#define RT5640_I2S_IF_SFT 12
/* ADC/DAC Clock Control 1 (0x73) */
#define RT5640_I2S_BCLK_MS1_MASK (0x1 << 15)
-#define RT5640_I2S_BCLK_MS1_SFT 15
+#define RT5640_I2S_BCLK_MS1_SFT 15
#define RT5640_I2S_BCLK_MS1_32 (0x0 << 15)
#define RT5640_I2S_BCLK_MS1_64 (0x1 << 15)
#define RT5640_I2S_PD1_MASK (0x7 << 12)
#define RT5640_I2S_PD1_12 (0x6 << 12)
#define RT5640_I2S_PD1_16 (0x7 << 12)
#define RT5640_I2S_BCLK_MS2_MASK (0x1 << 11)
-#define RT5640_I2S_BCLK_MS2_SFT 11
+#define RT5640_I2S_BCLK_MS2_SFT 11
#define RT5640_I2S_BCLK_MS2_32 (0x0 << 11)
#define RT5640_I2S_BCLK_MS2_64 (0x1 << 11)
#define RT5640_I2S_PD2_MASK (0x7 << 8)
#define RT5640_I2S_PD2_12 (0x6 << 8)
#define RT5640_I2S_PD2_16 (0x7 << 8)
#define RT5640_I2S_BCLK_MS3_MASK (0x1 << 7)
-#define RT5640_I2S_BCLK_MS3_SFT 7
+#define RT5640_I2S_BCLK_MS3_SFT 7
#define RT5640_I2S_BCLK_MS3_32 (0x0 << 7)
#define RT5640_I2S_BCLK_MS3_64 (0x1 << 7)
#define RT5640_I2S_PD3_MASK (0x7 << 4)
#define RT5640_ADC_R_OSR_64 (0x1 << 12)
#define RT5640_ADC_R_OSR_32 (0x2 << 12)
#define RT5640_ADC_R_OSR_16 (0x3 << 12)
-#define RT5640_DAHPF_EN (0x1 << 11)
+#define RT5640_DAHPF_EN (0x1 << 11)
#define RT5640_DAHPF_EN_SFT 11
-#define RT5640_ADHPF_EN (0x1 << 10)
+#define RT5640_ADHPF_EN (0x1 << 10)
#define RT5640_ADHPF_EN_SFT 10
/* Digital Microphone Control (0x75) */
#define RT5640_DMIC_2_EN_SFT 14
#define RT5640_DMIC_2_DIS (0x0 << 14)
#define RT5640_DMIC_2_EN (0x1 << 14)
-#define RT5640_DMIC_1L_LH_MASK (0x1 << 13)
+#define RT5640_DMIC_1L_LH_MASK (0x1 << 13)
#define RT5640_DMIC_1L_LH_SFT 13
#define RT5640_DMIC_1L_LH_FALLING (0x0 << 13)
#define RT5640_DMIC_1L_LH_RISING (0x1 << 13)
-#define RT5640_DMIC_1R_LH_MASK (0x1 << 12)
+#define RT5640_DMIC_1R_LH_MASK (0x1 << 12)
#define RT5640_DMIC_1R_LH_SFT 12
#define RT5640_DMIC_1R_LH_FALLING (0x0 << 12)
#define RT5640_DMIC_1R_LH_RISING (0x1 << 12)
#define RT5640_DMIC_2_DP_SFT 10
#define RT5640_DMIC_2_DP_GPIO4 (0x0 << 10)
#define RT5640_DMIC_2_DP_IN1N (0x1 << 10)
-#define RT5640_DMIC_2L_LH_MASK (0x1 << 9)
+#define RT5640_DMIC_2L_LH_MASK (0x1 << 9)
#define RT5640_DMIC_2L_LH_SFT 9
#define RT5640_DMIC_2L_LH_FALLING (0x0 << 9)
#define RT5640_DMIC_2L_LH_RISING (0x1 << 9)
-#define RT5640_DMIC_2R_LH_MASK (0x1 << 8)
+#define RT5640_DMIC_2R_LH_MASK (0x1 << 8)
#define RT5640_DMIC_2R_LH_SFT 8
#define RT5640_DMIC_2R_LH_FALLING (0x0 << 8)
#define RT5640_DMIC_2R_LH_RISING (0x1 << 8)
#define RT5640_SCLK_SRC_SFT 14
#define RT5640_SCLK_SRC_MCLK (0x0 << 14)
#define RT5640_SCLK_SRC_PLL1 (0x1 << 14)
-#define RT5640_SCLK_SRC_RCCLK (0x2 << 14) /* 15MHz */
#define RT5640_PLL1_SRC_MASK (0x3 << 12)
#define RT5640_PLL1_SRC_SFT 12
#define RT5640_PLL1_SRC_MCLK (0x0 << 12)
#define RT5640_AUTO_PD_SFT 8
#define RT5640_AUTO_PD_DIS (0x0 << 8)
#define RT5640_AUTO_PD_EN (0x1 << 8)
-#define RT5640_CLSD_OC_TH_MASK (0x3f)
+#define RT5640_CLSD_OC_TH_MASK (0x3f)
#define RT5640_CLSD_OC_TH_SFT 0
/* Class D Output Control (0x8d) */
-#define RT5640_CLSD_RATIO_MASK (0xf << 12)
+#define RT5640_CLSD_RATIO_MASK (0xf << 12)
#define RT5640_CLSD_RATIO_SFT 12
#define RT5640_CLSD_OM_MASK (0x1 << 11)
#define RT5640_CLSD_OM_SFT 11
#define RT5640_HP_CO_MASK (0x1 << 4)
#define RT5640_HP_CO_SFT 4
#define RT5640_HP_CO_DIS (0x0 << 4)
-#define RT5640_HP_CO_EN (0x1 << 4)
+#define RT5640_HP_CO_EN (0x1 << 4)
#define RT5640_HP_CP_MASK (0x1 << 3)
#define RT5640_HP_CP_SFT 3
-#define RT5640_HP_CP_PD (0x0 << 3)
-#define RT5640_HP_CP_PU (0x1 << 3)
+#define RT5640_HP_CP_PD (0x0 << 3)
+#define RT5640_HP_CP_PU (0x1 << 3)
#define RT5640_HP_SG_MASK (0x1 << 2)
#define RT5640_HP_SG_SFT 2
#define RT5640_HP_SG_DIS (0x0 << 2)
-#define RT5640_HP_SG_EN (0x1 << 2)
+#define RT5640_HP_SG_EN (0x1 << 2)
#define RT5640_HP_DP_MASK (0x1 << 1)
#define RT5640_HP_DP_SFT 1
-#define RT5640_HP_DP_PD (0x0 << 1)
-#define RT5640_HP_DP_PU (0x1 << 1)
+#define RT5640_HP_DP_PD (0x0 << 1)
+#define RT5640_HP_DP_PU (0x1 << 1)
#define RT5640_HP_CB_MASK (0x1)
#define RT5640_HP_CB_SFT 0
-#define RT5640_HP_CB_PD (0x0)
-#define RT5640_HP_CB_PU (0x1)
+#define RT5640_HP_CB_PD (0x0)
+#define RT5640_HP_CB_PU (0x1)
/* Depop Mode Control 2 (0x8f) */
#define RT5640_DEPOP_MASK (0x1 << 13)
#define RT5640_DEPOP_AUTO (0x0 << 13)
#define RT5640_DEPOP_MAN (0x1 << 13)
#define RT5640_RAMP_MASK (0x1 << 12)
-#define RT5640_RAMP_SFT 12
+#define RT5640_RAMP_SFT 12
#define RT5640_RAMP_DIS (0x0 << 12)
#define RT5640_RAMP_EN (0x1 << 12)
-#define RT5640_BPS_MASK (0x1 << 11)
+#define RT5640_BPS_MASK (0x1 << 11)
#define RT5640_BPS_SFT 11
#define RT5640_BPS_DIS (0x0 << 11)
#define RT5640_BPS_EN (0x1 << 11)
#define RT5640_MRES_25MO (0x1 << 8)
#define RT5640_MRES_35MO (0x2 << 8)
#define RT5640_MRES_45MO (0x3 << 8)
-#define RT5640_VLO_MASK (0x1 << 7)
+#define RT5640_VLO_MASK (0x1 << 7)
#define RT5640_VLO_SFT 7
#define RT5640_VLO_3V (0x0 << 7)
#define RT5640_VLO_32V (0x1 << 7)
#define RT5640_OSW_L_MASK (0x1 << 11)
#define RT5640_OSW_L_SFT 11
#define RT5640_OSW_L_DIS (0x0 << 11)
-#define RT5640_OSW_L_EN (0x1 << 11)
+#define RT5640_OSW_L_EN (0x1 << 11)
#define RT5640_OSW_R_MASK (0x1 << 10)
#define RT5640_OSW_R_SFT 10
#define RT5640_OSW_R_DIS (0x0 << 10)
-#define RT5640_OSW_R_EN (0x1 << 10)
+#define RT5640_OSW_R_EN (0x1 << 10)
#define RT5640_PM_HP_MASK (0x3 << 8)
#define RT5640_PM_HP_SFT 8
-#define RT5640_PM_HP_LV (0x0 << 8)
-#define RT5640_PM_HP_MV (0x1 << 8)
-#define RT5640_PM_HP_HV (0x2 << 8)
+#define RT5640_PM_HP_LV (0x0 << 8)
+#define RT5640_PM_HP_MV (0x1 << 8)
+#define RT5640_PM_HP_HV (0x2 << 8)
#define RT5640_IB_HP_MASK (0x3 << 6)
#define RT5640_IB_HP_SFT 6
#define RT5640_IB_HP_125IL (0x0 << 6)
#define RT5640_MIC1_OVCD_EN (0x1 << 11)
#define RT5640_MIC1_OVTH_MASK (0x3 << 9)
#define RT5640_MIC1_OVTH_SFT 9
-#define RT5640_MIC1_OVTH_600UA (0x0 << 9)
-#define RT5640_MIC1_OVTH_1500UA (0x1 << 9)
-#define RT5640_MIC1_OVTH_2000UA (0x2 << 9)
+#define RT5640_MIC1_OVTH_600UA (0x0 << 9)
+#define RT5640_MIC1_OVTH_1500UA (0x1 << 9)
+#define RT5640_MIC1_OVTH_2000UA (0x2 << 9)
#define RT5640_MIC2_OVCD_MASK (0x1 << 8)
#define RT5640_MIC2_OVCD_SFT 8
#define RT5640_MIC2_OVCD_DIS (0x0 << 8)
#define RT5640_MIC2_OVCD_EN (0x1 << 8)
#define RT5640_MIC2_OVTH_MASK (0x3 << 6)
#define RT5640_MIC2_OVTH_SFT 6
-#define RT5640_MIC2_OVTH_600UA (0x0 << 6)
-#define RT5640_MIC2_OVTH_1500UA (0x1 << 6)
-#define RT5640_MIC2_OVTH_2000UA (0x2 << 6)
+#define RT5640_MIC2_OVTH_600UA (0x0 << 6)
+#define RT5640_MIC2_OVTH_1500UA (0x1 << 6)
+#define RT5640_MIC2_OVTH_2000UA (0x2 << 6)
#define RT5640_PWR_MB_MASK (0x1 << 5)
#define RT5640_PWR_MB_SFT 5
#define RT5640_PWR_MB_PD (0x0 << 5)
#define RT5640_PWR_MB_PU (0x1 << 5)
-#define RT5640_PWR_CLK25M_MASK (0x1 << 4)
+#define RT5640_PWR_CLK25M_MASK (0x1 << 4)
#define RT5640_PWR_CLK25M_SFT 4
#define RT5640_PWR_CLK25M_PD (0x0 << 4)
#define RT5640_PWR_CLK25M_PU (0x1 << 4)
#define RT5640_EQ_CD_MASK (0x1 << 13)
#define RT5640_EQ_CD_SFT 13
#define RT5640_EQ_CD_DIS (0x0 << 13)
-#define RT5640_EQ_CD_EN (0x1 << 13)
+#define RT5640_EQ_CD_EN (0x1 << 13)
#define RT5640_EQ_DITH_MASK (0x3 << 8)
#define RT5640_EQ_DITH_SFT 8
#define RT5640_EQ_DITH_NOR (0x0 << 8)
#define RT5640_EQ_LPF_SFT 0
#define RT5640_EQ_LPF_DIS (0x0)
#define RT5640_EQ_LPF_EN (0x1)
-#define RT5640_EQ_CTRL_MASK (0x7f)
/* Memory Test (0xb2) */
#define RT5640_MT_MASK (0x1 << 15)
#define RT5640_DRC_AGC_DIS (0x0 << 14)
#define RT5640_DRC_AGC_EN (0x1 << 14)
#define RT5640_DRC_AGC_UPD (0x1 << 13)
-#define RT5640_DRC_AGC_UPD_BIT 13
-#define RT5640_DRC_AGC_AR_MASK (0x1f << 8)
+#define RT5640_DRC_AGC_UPD_BIT 13
+#define RT5640_DRC_AGC_AR_MASK (0x1f << 8)
#define RT5640_DRC_AGC_AR_SFT 8
#define RT5640_DRC_AGC_R_MASK (0x7 << 5)
#define RT5640_DRC_AGC_R_SFT 5
#define RT5640_DRC_AGC_R_192K (0x3 << 5)
#define RT5640_DRC_AGC_R_441K (0x5 << 5)
#define RT5640_DRC_AGC_R_882K (0x6 << 5)
-#define RT5640_DRC_AGC_R_1764K (0x7 << 5)
-#define RT5640_DRC_AGC_RC_MASK (0x1f)
+#define RT5640_DRC_AGC_R_1764K (0x7 << 5)
+#define RT5640_DRC_AGC_RC_MASK (0x1f)
#define RT5640_DRC_AGC_RC_SFT 0
/* DRC/AGC Control 2 (0xb5) */
-#define RT5640_DRC_AGC_POB_MASK (0x3f << 8)
-#define RT5640_DRC_AGC_POB_SFT 8
-#define RT5640_DRC_AGC_CP_MASK (0x1 << 7)
+#define RT5640_DRC_AGC_POB_MASK (0x3f << 8)
+#define RT5640_DRC_AGC_POB_SFT 8
+#define RT5640_DRC_AGC_CP_MASK (0x1 << 7)
#define RT5640_DRC_AGC_CP_SFT 7
#define RT5640_DRC_AGC_CP_DIS (0x0 << 7)
#define RT5640_DRC_AGC_CP_EN (0x1 << 7)
-#define RT5640_DRC_AGC_CPR_MASK (0x3 << 5)
-#define RT5640_DRC_AGC_CPR_SFT 5
-#define RT5640_DRC_AGC_CPR_1_1 (0x0 << 5)
-#define RT5640_DRC_AGC_CPR_1_2 (0x1 << 5)
-#define RT5640_DRC_AGC_CPR_1_3 (0x2 << 5)
-#define RT5640_DRC_AGC_CPR_1_4 (0x3 << 5)
-#define RT5640_DRC_AGC_PRB_MASK (0x1f)
-#define RT5640_DRC_AGC_PRB_SFT 0
+#define RT5640_DRC_AGC_CPR_MASK (0x3 << 5)
+#define RT5640_DRC_AGC_CPR_SFT 5
+#define RT5640_DRC_AGC_CPR_1_1 (0x0 << 5)
+#define RT5640_DRC_AGC_CPR_1_2 (0x1 << 5)
+#define RT5640_DRC_AGC_CPR_1_3 (0x2 << 5)
+#define RT5640_DRC_AGC_CPR_1_4 (0x3 << 5)
+#define RT5640_DRC_AGC_PRB_MASK (0x1f)
+#define RT5640_DRC_AGC_PRB_SFT 0
/* DRC/AGC Control 3 (0xb6) */
-#define RT5640_DRC_AGC_NGB_MASK (0xf << 12)
-#define RT5640_DRC_AGC_NGB_SFT 12
-#define RT5640_DRC_AGC_TAR_MASK (0x1f << 7)
-#define RT5640_DRC_AGC_TAR_SFT 7
-#define RT5640_DRC_AGC_NG_MASK (0x1 << 6)
+#define RT5640_DRC_AGC_NGB_MASK (0xf << 12)
+#define RT5640_DRC_AGC_NGB_SFT 12
+#define RT5640_DRC_AGC_TAR_MASK (0x1f << 7)
+#define RT5640_DRC_AGC_TAR_SFT 7
+#define RT5640_DRC_AGC_NG_MASK (0x1 << 6)
#define RT5640_DRC_AGC_NG_SFT 6
#define RT5640_DRC_AGC_NG_DIS (0x0 << 6)
#define RT5640_DRC_AGC_NG_EN (0x1 << 6)
-#define RT5640_DRC_AGC_NGH_MASK (0x1 << 5)
-#define RT5640_DRC_AGC_NGH_SFT 5
-#define RT5640_DRC_AGC_NGH_DIS (0x0 << 5)
+#define RT5640_DRC_AGC_NGH_MASK (0x1 << 5)
+#define RT5640_DRC_AGC_NGH_SFT 5
+#define RT5640_DRC_AGC_NGH_DIS (0x0 << 5)
#define RT5640_DRC_AGC_NGH_EN (0x1 << 5)
-#define RT5640_DRC_AGC_NGT_MASK (0x1f)
-#define RT5640_DRC_AGC_NGT_SFT 0
+#define RT5640_DRC_AGC_NGT_MASK (0x1f)
+#define RT5640_DRC_AGC_NGT_SFT 0
/* ANC Control 1 (0xb8) */
#define RT5640_ANC_M_MASK (0x1 << 15)
#define RT5640_ANC_M_SFT 15
#define RT5640_ANC_M_NOR (0x0 << 15)
#define RT5640_ANC_M_REV (0x1 << 15)
-#define RT5640_ANC_MASK (0x1 << 14)
+#define RT5640_ANC_MASK (0x1 << 14)
#define RT5640_ANC_SFT 14
#define RT5640_ANC_DIS (0x0 << 14)
#define RT5640_ANC_EN (0x1 << 14)
#define RT5640_JD_MO_MASK (0x1 << 5)
#define RT5640_JD_MO_SFT 5
#define RT5640_JD_MO_DIS (0x0 << 5)
-#define RT5640_JD_MO_EN (0x1 << 5)
+#define RT5640_JD_MO_EN (0x1 << 5)
#define RT5640_JD_MO_TRG_MASK (0x1 << 4)
#define RT5640_JD_MO_TRG_SFT 4
#define RT5640_JD_MO_TRG_LO (0x0 << 4)
#define RT5640_JD_P_INV (0x1 << 11)
#define RT5640_OT_P_MASK (0x1 << 10)
#define RT5640_OT_P_SFT 10
-#define RT5640_OT_P_NOR (0x0 << 10)
+#define RT5640_OT_P_NOR (0x0 << 10)
#define RT5640_OT_P_INV (0x1 << 10)
/* IRQ Control 2 (0xbe) */
-#define RT5640_IRQ_MB1_OC_MASK (0x1 << 15)
+#define RT5640_IRQ_MB1_OC_MASK (0x1 << 15)
#define RT5640_IRQ_MB1_OC_SFT 15
#define RT5640_IRQ_MB1_OC_BP (0x0 << 15)
#define RT5640_IRQ_MB1_OC_NOR (0x1 << 15)
-#define RT5640_IRQ_MB2_OC_MASK (0x1 << 14)
+#define RT5640_IRQ_MB2_OC_MASK (0x1 << 14)
#define RT5640_IRQ_MB2_OC_SFT 14
#define RT5640_IRQ_MB2_OC_BP (0x0 << 14)
#define RT5640_IRQ_MB2_OC_NOR (0x1 << 14)
-#define RT5640_MB1_OC_STKY_MASK (0x1 << 11)
-#define RT5640_MB1_OC_STKY_SFT 11
-#define RT5640_MB1_OC_STKY_DIS (0x0 << 11)
+#define RT5640_MB1_OC_STKY_MASK (0x1 << 11)
+#define RT5640_MB1_OC_STKY_SFT 11
+#define RT5640_MB1_OC_STKY_DIS (0x0 << 11)
#define RT5640_MB1_OC_STKY_EN (0x1 << 11)
-#define RT5640_MB2_OC_STKY_MASK (0x1 << 10)
-#define RT5640_MB2_OC_STKY_SFT 10
-#define RT5640_MB2_OC_STKY_DIS (0x0 << 10)
+#define RT5640_MB2_OC_STKY_MASK (0x1 << 10)
+#define RT5640_MB2_OC_STKY_SFT 10
+#define RT5640_MB2_OC_STKY_DIS (0x0 << 10)
#define RT5640_MB2_OC_STKY_EN (0x1 << 10)
#define RT5640_MB1_OC_P_MASK (0x1 << 7)
#define RT5640_MB1_OC_P_SFT 7
#define RT5640_DSP_CLK_192K (0x1 << 12)
#define RT5640_DSP_CLK_96K (0x2 << 12)
#define RT5640_DSP_CLK_64K (0x3 << 12)
-#define RT5640_DSP_PD_PIN_MASK (0x1 << 11)
+#define RT5640_DSP_PD_PIN_MASK (0x1 << 11)
#define RT5640_DSP_PD_PIN_SFT 11
#define RT5640_DSP_PD_PIN_LO (0x0 << 11)
#define RT5640_DSP_PD_PIN_HI (0x1 << 11)
-#define RT5640_DSP_RST_PIN_MASK (0x1 << 10)
+#define RT5640_DSP_RST_PIN_MASK (0x1 << 10)
#define RT5640_DSP_RST_PIN_SFT 10
#define RT5640_DSP_RST_PIN_LO (0x0 << 10)
#define RT5640_DSP_RST_PIN_HI (0x1 << 10)
#define RT5640_DSP_R_EN (0x1 << 9)
-#define RT5640_DSP_W_EN (0x1 << 8)
+#define RT5640_DSP_R_EN_BIT 9
+#define RT5640_DSP_W_EN (0x1 << 8)
+#define RT5640_DSP_W_EN_BIT 8
#define RT5640_DSP_CMD_MASK (0xff)
-#define RT5640_DSP_CMD_PE (0x0d) /* Patch Entry */
-#define RT5640_DSP_CMD_MW (0x3b) /* Memory Write */
+#define RT5640_DSP_CMD_SFT 0
+#define RT5640_DSP_CMD_MW (0x3B) /* Memory Write */
#define RT5640_DSP_CMD_MR (0x37) /* Memory Read */
#define RT5640_DSP_CMD_RR (0x60) /* Register Read */
#define RT5640_DSP_CMD_RW (0x68) /* Register Write */
-#define RT5640_DSP_REG_DATHI (0x26) /* High Data Addr */
-#define RT5640_DSP_REG_DATLO (0x25) /* Low Data Addr */
/* Programmable Register Array Control 1 (0xc8) */
#define RT5640_REG_SEQ_MASK (0xf << 12)
#define RT5640_SEQ2_PT_RUN_BIT 5
/* Programmable Register Array Control 4 (0xcb) */
-#define RT5640_SEQ1_START_MASK (0xf << 8)
+#define RT5640_SEQ1_START_MASK (0xf << 8)
#define RT5640_SEQ1_START_SFT 8
#define RT5640_SEQ1_END_MASK (0xf)
#define RT5640_SEQ1_END_SFT 0
/* Programmable Register Array Control 5 (0xcc) */
-#define RT5640_SEQ2_START_MASK (0xf << 8)
+#define RT5640_SEQ2_START_MASK (0xf << 8)
#define RT5640_SEQ2_START_SFT 8
#define RT5640_SEQ2_END_MASK (0xf)
#define RT5640_SEQ2_END_SFT 0
#define RT5640_SCB_SWAP_SFT 15
#define RT5640_SCB_SWAP_DIS (0x0 << 15)
#define RT5640_SCB_SWAP_EN (0x1 << 15)
-#define RT5640_SCB_MASK (0x1 << 14)
+#define RT5640_SCB_MASK (0x1 << 14)
#define RT5640_SCB_SFT 14
#define RT5640_SCB_DIS (0x0 << 14)
#define RT5640_SCB_EN (0x1 << 14)
#define RT5640_M_BB_L_SFT 9
#define RT5640_M_BB_R_MASK (0x1 << 8)
#define RT5640_M_BB_R_SFT 8
-#define RT5640_M_BB_HPF_L_MASK (0x1 << 7)
+#define RT5640_M_BB_HPF_L_MASK (0x1 << 7)
#define RT5640_M_BB_HPF_L_SFT 7
-#define RT5640_M_BB_HPF_R_MASK (0x1 << 6)
+#define RT5640_M_BB_HPF_R_MASK (0x1 << 6)
#define RT5640_M_BB_HPF_R_SFT 6
#define RT5640_G_BB_BST_MASK (0x3f)
#define RT5640_G_BB_BST_SFT 0
#define RT5640_M_MP3_MASK (0x1 << 13)
#define RT5640_M_MP3_SFT 13
#define RT5640_M_MP3_DIS (0x0 << 13)
-#define RT5640_M_MP3_EN (0x1 << 13)
+#define RT5640_M_MP3_EN (0x1 << 13)
#define RT5640_EG_MP3_MASK (0x1f << 8)
#define RT5640_EG_MP3_SFT 8
#define RT5640_MP3_HLP_MASK (0x1 << 7)
#define RT5640_MP3_HLP_SFT 7
#define RT5640_MP3_HLP_DIS (0x0 << 7)
#define RT5640_MP3_HLP_EN (0x1 << 7)
-#define RT5640_M_MP3_ORG_L_MASK (0x1 << 6)
-#define RT5640_M_MP3_ORG_L_SFT 6
-#define RT5640_M_MP3_ORG_R_MASK (0x1 << 5)
-#define RT5640_M_MP3_ORG_R_SFT 5
+#define RT5640_M_MP3_ORG_L_MASK (0x1 << 6)
+#define RT5640_M_MP3_ORG_L_SFT 6
+#define RT5640_M_MP3_ORG_R_MASK (0x1 << 5)
+#define RT5640_M_MP3_ORG_R_SFT 5
/* MP3 Plus Control 2 (0xd1) */
#define RT5640_MP3_WT_MASK (0x1 << 13)
#define RT5640_3D_CF_MASK (0x1 << 15)
#define RT5640_3D_CF_SFT 15
#define RT5640_3D_CF_DIS (0x0 << 15)
-#define RT5640_3D_CF_EN (0x1 << 15)
+#define RT5640_3D_CF_EN (0x1 << 15)
#define RT5640_3D_HP_MASK (0x1 << 14)
#define RT5640_3D_HP_SFT 14
#define RT5640_3D_HP_DIS (0x0 << 14)
-#define RT5640_3D_HP_EN (0x1 << 14)
+#define RT5640_3D_HP_EN (0x1 << 14)
#define RT5640_3D_BT_MASK (0x1 << 13)
#define RT5640_3D_BT_SFT 13
#define RT5640_3D_BT_DIS (0x0 << 13)
#define RT5640_CAL_M_SFT 4
#define RT5640_CAL_M_DEP (0x0 << 4)
#define RT5640_CAL_M_CAL (0x1 << 4)
-#define RT5640_CAL_MASK (0x1 << 3)
+#define RT5640_CAL_MASK (0x1 << 3)
#define RT5640_CAL_SFT 3
#define RT5640_CAL_DIS (0x0 << 3)
#define RT5640_CAL_EN (0x1 << 3)
#define RT5640_HP_SV_MASK (0x1 << 12)
#define RT5640_HP_SV_SFT 12
#define RT5640_HP_SV_DIS (0x0 << 12)
-#define RT5640_HP_SV_EN (0x1 << 12)
+#define RT5640_HP_SV_EN (0x1 << 12)
#define RT5640_ZCD_DIG_MASK (0x1 << 11)
#define RT5640_ZCD_DIG_SFT 11
#define RT5640_ZCD_DIG_DIS (0x0 << 11)
#define RT5640_ZCD_DIG_EN (0x1 << 11)
-#define RT5640_ZCD_MASK (0x1 << 10)
+#define RT5640_ZCD_MASK (0x1 << 10)
#define RT5640_ZCD_SFT 10
#define RT5640_ZCD_PD (0x0 << 10)
#define RT5640_ZCD_PU (0x1 << 10)
#define RT5640_3D_SPK_SG_SFT 0
/* Wind Noise Detection Control 1 (0x6c) */
-#define RT5640_WND_MASK (0x1 << 15)
+#define RT5640_WND_MASK (0x1 << 15)
#define RT5640_WND_SFT 15
#define RT5640_WND_DIS (0x0 << 15)
#define RT5640_WND_EN (0x1 << 15)
/* Wind Noise Detection Control 2 (0x6d) */
-#define RT5640_WND_FC_NW_MASK (0x3f << 10)
+#define RT5640_WND_FC_NW_MASK (0x3f << 10)
#define RT5640_WND_FC_NW_SFT 10
-#define RT5640_WND_FC_WK_MASK (0x3f << 4)
+#define RT5640_WND_FC_WK_MASK (0x3f << 4)
#define RT5640_WND_FC_WK_SFT 4
/* Wind Noise Detection Control 3 (0x6e) */
#define RT5640_WND_FC_ST_SFT 0
/* Wind Noise Detection Control 4 (0x6f) */
-#define RT5640_WND_TH_LO_MASK (0x3ff)
+#define RT5640_WND_TH_LO_MASK (0x3ff)
#define RT5640_WND_TH_LO_SFT 0
/* Wind Noise Detection Control 5 (0x70) */
/* Wind Noise Detection Control 8 (0x73) */
#define RT5640_WND_WIND_MASK (0x1 << 13) /* Read-Only */
#define RT5640_WND_WIND_SFT 13
-#define RT5640_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
+#define RT5640_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
#define RT5640_WND_STRONG_SFT 12
enum {
RT5640_NO_WIND,
#define RT5640_DP_SPK_EN (0x1 << 10)
/* EQ Pre Volume Control (0xb3) */
-#define RT5640_EQ_PRE_VOL_MASK (0xffff)
+#define RT5640_EQ_PRE_VOL_MASK (0xffff)
#define RT5640_EQ_PRE_VOL_SFT 0
/* EQ Post Volume Control (0xb4) */
-#define RT5640_EQ_PST_VOL_MASK (0xffff)
+#define RT5640_EQ_PST_VOL_MASK (0xffff)
#define RT5640_EQ_PST_VOL_SFT 0
-/* General Control1 (0xfa) */
-#define RT5640_M_MAMIX_L (0x1 << 13)
-#define RT5640_M_MAMIX_R (0x1 << 12)
-
-/* General Control2 (0xfb) */
-#define RT5640_RXDC_SRC_MASK (0x1 << 7)
-#define RT5640_RXDC_SRC_STO (0x0 << 7)
-#define RT5640_RXDC_SRC_MONO (0x1 << 7)
-#define RT5640_RXDC_SRC_SFT (7)
-#define RT5640_RXDP2_SEL_MASK (0x1 << 3)
-#define RT5640_RXDP2_SEL_IF2 (0x0 << 3)
-#define RT5640_RXDP2_SEL_ADC (0x1 << 3)
-#define RT5640_RXDP2_SEL_SFT (3)
-
-
-/* Vendor ID (0xfd) */
-#define RT5640_VER_C 0x2
-#define RT5640_VER_D 0x3
-
-
-/* Volume Rescale */
-#define RT5640_VOL_RSCL_MAX 0x27
-#define RT5640_VOL_RSCL_RANGE 0x1F
-/* Debug String Length */
-#define RT5640_REG_DISP_LEN 23
-
#define RT5640_NO_JACK BIT(0)
#define RT5640_HEADSET_DET BIT(1)
#define RT5640_HEADPHO_DET BIT(2)
-int rt5640_headset_detect(struct snd_soc_codec *codec, int jack_insert);
+/* General Control1 (0xfa) */
+#define RT5640_M_MAMIX_L (0x1 << 13)
+#define RT5640_M_MAMIX_R (0x1 << 12)
/* System Clock Source */
-enum {
- RT5640_SCLK_S_MCLK,
- RT5640_SCLK_S_PLL1,
- RT5640_SCLK_S_RCCLK,
-};
+#define RT5640_SCLK_S_MCLK 0
+#define RT5640_SCLK_S_PLL1 1
+#define RT5640_SCLK_S_PLL1_TK 2
+#define RT5640_SCLK_S_RCCLK 3
/* PLL1 Source */
-enum {
- RT5640_PLL1_S_MCLK,
- RT5640_PLL1_S_BCLK1,
- RT5640_PLL1_S_BCLK2,
- RT5640_PLL1_S_BCLK3,
-};
+#define RT5640_PLL1_S_MCLK 0
+#define RT5640_PLL1_S_BCLK1 1
+#define RT5640_PLL1_S_BCLK2 2
+#define RT5640_PLL1_S_BCLK3 3
+
enum {
RT5640_AIF1,
RT5640_AIFS,
};
-#define RT5640_U_IF1 (0x1)
-#define RT5640_U_IF2 (0x1 << 1)
-#define RT5640_U_IF3 (0x1 << 2)
+enum {
+ RT5640_U_IF1 = 0x1,
+ RT5640_U_IF2 = 0x2,
+ RT5640_U_IF3 = 0x4,
+};
enum {
RT5640_IF_123,
RT5640_DMIC2,
};
-struct rt5640_pll_code {
- bool m_bp; /* Indicates bypass m code or not. */
- int m_code;
- int n_code;
- int k_code;
-};
-
struct rt5640_priv {
struct snd_soc_codec *codec;
- struct delayed_work patch_work;
-
- int aif_pu;
+ struct rt5640_platform_data pdata;
+ struct regmap *regmap;
+ struct clk *mclk;
+ struct work_struct work;
+ struct workqueue_struct *wq;
int sysclk;
int sysclk_src;
int lrck[RT5640_AIFS];
int pll_in;
int pll_out;
- int dmic_en;
- int dsp_sw; /* expected parameter setting */
- bool dsp_play_pass;
- bool dsp_rec_pass;
+ bool hp_mute;
+
+ struct delayed_work adc_poll_work;
+ struct iio_channel *chan;
+ int hp_det_adc_value;
+ bool hp_insert;
+ int hp_con_gpio;
+ bool hp_con_gpio_active_high;
+ struct delayed_work init_delayed_work;
+ struct delayed_work aux_det_work;
+ int aux_det_gpio;
+ int aux_det_irq;
+ struct snd_soc_jack hp_jack;
};
-int rt5640_conn_mux_path(struct snd_soc_codec *codec,
- char *widget_name, char *path_name);
+int rt5640_dmic_enable(struct snd_soc_codec *codec,
+ bool dmic1_data_pin, bool dmic2_data_pin);
-#endif /* __RT5640_H__ */
+#endif
projects / firefly-linux-kernel-4.4.55.git / blobdiff