[Hexagon] Use A2_tfrsi for constant pool and jump table addresses

[oota-llvm.git] / test / CodeGen / AArch64 / 128bit_load_store.ll

diff --git a/test/CodeGen/AArch64/128bit_load_store.ll b/test/CodeGen/AArch64/128bit_load_store.ll
index 2360e858b574c8a9adbff15f91e067e621b4e5e1..94fd386e0eaf542f2694b66022b1df1699e3ae1a 100644 (file)
--- a/test/CodeGen/AArch64/128bit_load_store.ll
+++ b/test/CodeGen/AArch64/128bit_load_store.ll
@@ -1,5 +1,4 @@
-; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=neon| FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
-; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=neon | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM64
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=neon | FileCheck %s --check-prefix=CHECK
 
 define void @test_store_f128(fp128* %ptr, fp128 %val) #0 {
 ; CHECK-LABEL: test_store_f128
@@ -13,17 +12,14 @@ define fp128 @test_load_f128(fp128* readonly %ptr) #2 {
 ; CHECK-LABEL: test_load_f128
 ; CHECK: ldr    {{q[0-9]+}}, [{{x[0-9]+}}]
 entry:
-  %0 = load fp128* %ptr, align 16
+  %0 = load fp128, fp128* %ptr, align 16
   ret fp128 %0
 }
 
 define void @test_vstrq_p128(i128* %ptr, i128 %val) #0 {
-; CHECK-ARM64-LABEL: test_vstrq_p128
-; CHECK-ARM64: stp {{x[0-9]+}}, {{x[0-9]+}}, [{{x[0-9]+}}]
+; CHECK-LABEL: test_vstrq_p128
+; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [{{x[0-9]+}}]
 
-; CHECK-AARCH64-LABEL: test_vstrq_p128
-; CHECK-AARCH64: str {{x[0-9]+}}, [{{x[0-9]+}}, #8]
-; CHECK-AARCH64: str {{x[0-9]+}}, [{{x[0-9]+}}]
 entry:
   %0 = bitcast i128* %ptr to fp128*
   %1 = bitcast i128 %val to fp128
@@ -32,15 +28,12 @@ entry:
 }
 
 define i128 @test_vldrq_p128(i128* readonly %ptr) #2 {
-; CHECK-ARM64-LABEL: test_vldrq_p128
-; CHECK-ARM64: ldp {{x[0-9]+}}, {{x[0-9]+}}, [{{x[0-9]+}}]
+; CHECK-LABEL: test_vldrq_p128
+; CHECK: ldp {{x[0-9]+}}, {{x[0-9]+}}, [{{x[0-9]+}}]
 
-; CHECK-AARCH64-LABEL: test_vldrq_p128
-; CHECK-AARCH64: ldr {{x[0-9]+}}, [{{x[0-9]+}}]
-; CHECK-AARCH64: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #8]
 entry:
   %0 = bitcast i128* %ptr to fp128*
-  %1 = load fp128* %0, align 16
+  %1 = load fp128, fp128* %0, align 16
   %2 = bitcast fp128 %1 to i128
   ret i128 %2
 }
@@ -51,8 +44,8 @@ define void @test_ld_st_p128(i128* nocapture %ptr) #0 {
 ; CHECK-NEXT: str      {{q[0-9]+}}, [{{x[0-9]+}}, #16]
 entry:
   %0 = bitcast i128* %ptr to fp128*
-  %1 = load fp128* %0, align 16
-  %add.ptr = getelementptr inbounds i128* %ptr, i64 1
+  %1 = load fp128, fp128* %0, align 16
+  %add.ptr = getelementptr inbounds i128, i128* %ptr, i64 1
   %2 = bitcast i128* %add.ptr to fp128*
   store fp128 %1, fp128* %2, align 16
   ret void