[AArch64] Don't assert when combining (v3f32 select (setcc f64)).

[oota-llvm.git] / test / CodeGen / AArch64 / aarch64-be-bv.ll

diff --git a/test/CodeGen/AArch64/aarch64-be-bv.ll b/test/CodeGen/AArch64/aarch64-be-bv.ll
index 45eca5916d6a38564391373e66a9f77732d4b60f..fb41156c09dfd39a1178b94a05bde1f57cea01bc 100644 (file)
--- a/test/CodeGen/AArch64/aarch64-be-bv.ll
+++ b/test/CodeGen/AArch64/aarch64-be-bv.ll
@@ -8,7 +8,7 @@ define i16 @movi_modimm_t1() nounwind {
   ; CHECK-NEXT:    movi           v[[REG2:[0-9]+]].4s, #0x1
   ; CHECK-NEXT:    add    v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -20,7 +20,7 @@ define i16 @movi_modimm_t2() nounwind {
   ; CHECK-NEXT:    movi           v[[REG2:[0-9]+]].4s, #0x1, lsl #8
   ; CHECK-NEXT:    add    v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 256, i16 0, i16 256, i16 0, i16 256, i16 0, i16 256, i16 0>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -32,7 +32,7 @@ define i16 @movi_modimm_t3() nounwind {
   ; CHECK-NEXT:    movi           v[[REG2:[0-9]+]].4s, #0x1, lsl #16
   ; CHECK-NEXT:    add    v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -44,7 +44,7 @@ define i16 @movi_modimm_t4() nounwind {
   ; CHECK-NEXT:    movi           v[[REG2:[0-9]+]].4s, #0x1, lsl #24
   ; CHECK-NEXT:    add    v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 0, i16 256, i16 0, i16 256, i16 0, i16 256, i16 0, i16 256>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -56,7 +56,7 @@ define i16 @movi_modimm_t5() nounwind {
   ; CHECK-NEXT:    movi           v[[REG2:[0-9]+]].8h, #0x1
   ; CHECK-NEXT:    add    v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -68,7 +68,7 @@ define i16 @movi_modimm_t6() nounwind {
   ; CHECK-NEXT:    movi           v[[REG2:[0-9]+]].8h, #0x1, lsl #8
   ; CHECK-NEXT:    add    v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -80,7 +80,7 @@ define i16 @movi_modimm_t7() nounwind {
   ; CHECK-NEXT:    movi           v[[REG2:[0-9]+]].4s, #0x1, msl #8
   ; CHECK-NEXT:    add    v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 511, i16 0, i16 511, i16 0, i16 511, i16 0, i16 511, i16 0>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -92,7 +92,7 @@ define i16 @movi_modimm_t8() nounwind {
   ; CHECK-NEXT:    movi           v[[REG2:[0-9]+]].4s, #0x1, msl #16
   ; CHECK-NEXT:    add    v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 65535, i16 1, i16 65535, i16 1, i16 65535, i16 1, i16 65535, i16 1>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -104,7 +104,7 @@ define i16 @movi_modimm_t9() nounwind {
   ; CHECK-NEXT:    movi           v[[REG2:[0-9]+]].16b, #0x1
   ; CHECK-NEXT:    add    v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -116,7 +116,7 @@ define i16 @movi_modimm_t10() nounwind {
   ; CHECK-NEXT:    movi           v[[REG2:[0-9]+]].2d, #0x00ffff0000ffff
   ; CHECK-NEXT:    add    v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 -1, i16 0, i16 -1, i16 0, i16 -1, i16 0, i16 -1, i16 0>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -128,7 +128,7 @@ define i16 @fmov_modimm_t11() nounwind {
   ; CHECK-NEXT:    fmov    v[[REG2:[0-9]+]].4s, #3.00000000
   ; CHECK-NEXT:    add    v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 0, i16 16448, i16 0, i16 16448, i16 0, i16 16448, i16 0, i16 16448>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -140,7 +140,7 @@ define i16 @fmov_modimm_t12() nounwind {
   ; CHECK-NEXT:    fmov    v[[REG2:[0-9]+]].2d, #0.17968750
   ; CHECK-NEXT:    add    v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 0, i16 0, i16 0, i16 16327, i16 0, i16 0, i16 0, i16 16327>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -152,7 +152,7 @@ define i16 @mvni_modimm_t1() nounwind {
   ; CHECK-NEXT:    mvni           v[[REG2:[0-9]+]].4s, #0x1
   ; CHECK-NEXT:    add    v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -164,7 +164,7 @@ define i16 @mvni_modimm_t2() nounwind {
   ; CHECK-NEXT:    mvni           v[[REG2:[0-9]+]].4s, #0x1, lsl #8
   ; CHECK-NEXT:    add    v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -176,7 +176,7 @@ define i16 @mvni_modimm_t3() nounwind {
   ; CHECK-NEXT:    mvni           v[[REG2:[0-9]+]].4s, #0x1, lsl #16
   ; CHECK-NEXT:    add    v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -188,7 +188,7 @@ define i16 @mvni_modimm_t4() nounwind {
   ; CHECK-NEXT:    mvni           v[[REG2:[0-9]+]].4s, #0x1, lsl #24
   ; CHECK-NEXT:    add    v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -200,7 +200,7 @@ define i16 @mvni_modimm_t5() nounwind {
   ; CHECK-NEXT:    mvni           v[[REG2:[0-9]+]].8h, #0x1
   ; CHECK-NEXT:    add    v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -212,7 +212,7 @@ define i16 @mvni_modimm_t6() nounwind {
   ; CHECK-NEXT:    mvni           v[[REG2:[0-9]+]].8h, #0x1, lsl #8
   ; CHECK-NEXT:    add    v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -224,7 +224,7 @@ define i16 @mvni_modimm_t7() nounwind {
   ; CHECK-NEXT:    mvni           v[[REG2:[0-9]+]].4s, #0x1, msl #8
   ; CHECK-NEXT:    add    v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 65024, i16 65535, i16 65024, i16 65535, i16 65024, i16 65535, i16 65024, i16 65535>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -236,7 +236,7 @@ define i16 @mvni_modimm_t8() nounwind {
   ; CHECK-NEXT:    mvni           v[[REG2:[0-9]+]].4s, #0x1, msl #16
   ; CHECK-NEXT:    add    v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = add <8 x i16> %in, <i16 0, i16 65534, i16 0, i16 65534, i16 0, i16 65534, i16 0, i16 65534>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -247,7 +247,7 @@ define i16 @bic_modimm_t1() nounwind {
   ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
   ; CHECK-NEXT:    bic    v[[REG2:[0-9]+]].4s, #0x1
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = and <8 x i16> %in, <i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -258,7 +258,7 @@ define i16 @bic_modimm_t2() nounwind {
   ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
   ; CHECK-NEXT:    bic    v[[REG2:[0-9]+]].4s, #0x1, lsl #8
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = and <8 x i16> %in, <i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -269,7 +269,7 @@ define i16 @bic_modimm_t3() nounwind {
   ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
   ; CHECK-NEXT:    bic    v[[REG2:[0-9]+]].4s, #0x1, lsl #16
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = and <8 x i16> %in, <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -280,7 +280,7 @@ define i16 @bic_modimm_t4() nounwind {
   ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
   ; CHECK-NEXT:    bic    v[[REG2:[0-9]+]].4s, #0x1, lsl #24
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = and <8 x i16> %in, <i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -291,7 +291,7 @@ define i16 @bic_modimm_t5() nounwind {
   ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
   ; CHECK-NEXT:    bic    v[[REG2:[0-9]+]].8h, #0x1
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = and <8 x i16> %in, <i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -302,7 +302,7 @@ define i16 @bic_modimm_t6() nounwind {
   ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
   ; CHECK-NEXT:    bic    v[[REG2:[0-9]+]].8h, #0x1, lsl #8
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = and <8 x i16> %in, <i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -313,7 +313,7 @@ define i16 @orr_modimm_t1() nounwind {
   ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
   ; CHECK-NEXT:    orr    v[[REG2:[0-9]+]].4s, #0x1
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = or <8 x i16> %in, <i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -324,7 +324,7 @@ define i16 @orr_modimm_t2() nounwind {
   ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
   ; CHECK-NEXT:    orr     v[[REG2:[0-9]+]].4s, #0x1, lsl #8
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = or <8 x i16> %in, <i16 256, i16 0, i16 256, i16 0, i16 256, i16 0, i16 256, i16 0>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -335,7 +335,7 @@ define i16 @orr_modimm_t3() nounwind {
   ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
   ; CHECK-NEXT:    orr    v[[REG2:[0-9]+]].4s, #0x1, lsl #16
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = or <8 x i16> %in, <i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -346,7 +346,7 @@ define i16 @orr_modimm_t4() nounwind {
   ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
   ; CHECK-NEXT:    orr    v[[REG2:[0-9]+]].4s, #0x1, lsl #24
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = or <8 x i16> %in, <i16 0, i16 256, i16 0, i16 256, i16 0, i16 256, i16 0, i16 256>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -357,7 +357,7 @@ define i16 @orr_modimm_t5() nounwind {
   ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
   ; CHECK-NEXT:    orr    v[[REG2:[0-9]+]].8h, #0x1
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = or <8 x i16> %in, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -368,7 +368,7 @@ define i16 @orr_modimm_t6() nounwind {
   ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
   ; CHECK-NEXT:    orr    v[[REG2:[0-9]+]].8h, #0x1, lsl #8
   ; CHECK-NEXT:    umov           w{{[0-9]+}}, v[[REG1]].h[0]
-  %in = load <8 x i16>* @vec_v8i16
+  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
   %rv = or <8 x i16> %in, <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256>
   %el = extractelement <8 x i16> %rv, i32 0
   ret i16 %el
@@ -377,9 +377,11 @@ define i16 @orr_modimm_t6() nounwind {
 declare i8 @f_v8i8(<8 x i8> %arg)
 declare i16 @f_v4i16(<4 x i16> %arg)
 declare i32 @f_v2i32(<2 x i32> %arg)
+declare i64 @f_v1i64(<1 x i64> %arg)
 declare i8 @f_v16i8(<16 x i8> %arg)
 declare i16 @f_v8i16(<8 x i16> %arg)
 declare i32 @f_v4i32(<4 x i32> %arg)
+declare i64 @f_v2i64(<2 x i64> %arg)
 
 ; CHECK-LABEL: modimm_t1_call:
 define void @modimm_t1_call() {
@@ -395,6 +397,9 @@ define void @modimm_t1_call() {
   ; CHECK-NEXT:    rev64   v{{[0-9]+}}.2s, v[[REG1]].2s
   ; CHECK-NEXT:    bl      f_v2i32
   call i32 @f_v2i32(<2 x i32> <i32 6, i32 6>)
+  ; CHECK:         movi    v{{[0-9]+}}.2s, #0x5
+  ; CHECK-NEXT:    bl      f_v1i64
+  call i64 @f_v1i64(<1 x i64> <i64 21474836485>)
   ; CHECK:         movi    v[[REG1:[0-9]+]].4s, #0x5
   ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].16b, v[[REG1]].16b
   ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
@@ -410,6 +415,10 @@ define void @modimm_t1_call() {
   ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
   ; CHECK-NEXT:    bl      f_v4i32
   call i32 @f_v4i32(<4 x i32> <i32 3, i32 3, i32 3, i32 3>)
+  ; CHECK:         movi    v[[REG:[0-9]+]].4s, #0x2
+  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
+  ; CHECK-NEXT:    bl      f_v2i64
+  call i64 @f_v2i64(<2 x i64> <i64 8589934594, i64 8589934594>)
 
   ret void
 }
@@ -428,6 +437,9 @@ define void @modimm_t2_call() {
   ; CHECK-NEXT:    rev64   v{{[0-9]+}}.2s, v[[REG1]].2s
   ; CHECK-NEXT:    bl      f_v2i32
   call i32 @f_v2i32(<2 x i32> <i32 1536, i32 1536>)
+  ; CHECK:         movi    v{{[0-9]+}}.2s, #0x5, lsl #8
+  ; CHECK-NEXT:    bl      f_v1i64
+  call i64 @f_v1i64(<1 x i64> <i64 5497558140160>)
   ; CHECK:         movi    v[[REG1:[0-9]+]].4s, #0x5, lsl #8
   ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].16b, v[[REG1]].16b
   ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
@@ -443,6 +455,10 @@ define void @modimm_t2_call() {
   ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
   ; CHECK-NEXT:    bl      f_v4i32
   call i32 @f_v4i32(<4 x i32> <i32 768, i32 768, i32 768, i32 768>)
+  ; CHECK:         movi    v[[REG:[0-9]+]].4s, #0x2, lsl #8
+  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
+  ; CHECK-NEXT:    bl      f_v2i64
+  call i64 @f_v2i64(<2 x i64> <i64 2199023256064, i64 2199023256064>)
 
   ret void
 }
@@ -461,6 +477,9 @@ define void @modimm_t3_call() {
   ; CHECK-NEXT:    rev64   v{{[0-9]+}}.2s, v[[REG1]].2s
   ; CHECK-NEXT:    bl      f_v2i32
   call i32 @f_v2i32(<2 x i32> <i32 393216, i32 393216>)
+  ; CHECK:         movi    v{{[0-9]+}}.2s, #0x5, lsl #16
+  ; CHECK-NEXT:    bl      f_v1i64
+  call i64 @f_v1i64(<1 x i64> <i64 1407374883880960>)
   ; CHECK:         movi    v[[REG1:[0-9]+]].4s, #0x5, lsl #16
   ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].16b, v[[REG1]].16b
   ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
@@ -476,6 +495,10 @@ define void @modimm_t3_call() {
   ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
   ; CHECK-NEXT:    bl      f_v4i32
   call i32 @f_v4i32(<4 x i32> <i32 196608, i32 196608, i32 196608, i32 196608>)
+  ; CHECK:         movi    v[[REG:[0-9]+]].4s, #0x2, lsl #16
+  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
+  ; CHECK-NEXT:    bl      f_v2i64
+  call i64 @f_v2i64(<2 x i64> <i64 562949953552384, i64 562949953552384>)
 
   ret void
 }
@@ -494,6 +517,9 @@ define void @modimm_t4_call() {
   ; CHECK-NEXT:    rev64   v{{[0-9]+}}.2s, v[[REG1]].2s
   ; CHECK-NEXT:    bl      f_v2i32
   call i32 @f_v2i32(<2 x i32> <i32 100663296, i32 100663296>)
+  ; CHECK:         movi    v{{[0-9]+}}.2s, #0x5, lsl #24
+  ; CHECK-NEXT:    bl      f_v1i64
+  call i64 @f_v1i64(<1 x i64> <i64 360287970273525760>)
   ; CHECK:         movi    v[[REG1:[0-9]+]].4s, #0x5, lsl #24
   ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].16b, v[[REG1]].16b
   ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
@@ -509,6 +535,10 @@ define void @modimm_t4_call() {
   ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
   ; CHECK-NEXT:    bl      f_v4i32
   call i32 @f_v4i32(<4 x i32> <i32 50331648, i32 50331648, i32 50331648, i32 50331648>)
+  ; CHECK:         movi    v[[REG:[0-9]+]].4s, #0x2, lsl #24
+  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
+  ; CHECK-NEXT:    bl      f_v2i64
+  call i64 @f_v2i64(<2 x i64> <i64 144115188109410304, i64 144115188109410304>)
 
   ret void
 }
@@ -527,6 +557,9 @@ define void @modimm_t5_call() {
   ; CHECK-NEXT:    rev64   v{{[0-9]+}}.2s, v[[REG1]].2s
   ; CHECK-NEXT:    bl      f_v2i32
   call i32 @f_v2i32(<2 x i32> <i32 393222, i32 393222>)
+  ; CHECK:         movi    v{{[0-9]+}}.4h, #0x5
+  ; CHECK-NEXT:    bl      f_v1i64
+  call i64 @f_v1i64(<1 x i64> <i64 1407396358717445>)
   ; CHECK:         movi    v[[REG1:[0-9]+]].8h, #0x5
   ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].16b, v[[REG1]].16b
   ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
@@ -542,6 +575,10 @@ define void @modimm_t5_call() {
   ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
   ; CHECK-NEXT:    bl      f_v4i32
   call i32 @f_v4i32(<4 x i32> <i32 196611, i32 196611, i32 196611, i32 196611>)
+  ; CHECK:         movi    v[[REG:[0-9]+]].8h, #0x2
+  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
+  ; CHECK-NEXT:    bl      f_v2i64
+  call i64 @f_v2i64(<2 x i64> <i64 562958543486978, i64 562958543486978>)
 
   ret void
 }
@@ -560,6 +597,9 @@ define void @modimm_t6_call() {
   ; CHECK-NEXT:    rev64   v{{[0-9]+}}.2s, v[[REG1]].2s
   ; CHECK-NEXT:    bl      f_v2i32
   call i32 @f_v2i32(<2 x i32> <i32 100664832, i32 100664832>)
+  ; CHECK:         movi    v{{[0-9]+}}.4h, #0x5, lsl #8
+  ; CHECK-NEXT:    bl      f_v1i64
+  call i64 @f_v1i64(<1 x i64> <i64 360293467831665920>)
   ; CHECK:         movi    v[[REG1:[0-9]+]].8h, #0x5, lsl #8
   ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].16b, v[[REG1]].16b
   ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
@@ -575,6 +615,10 @@ define void @modimm_t6_call() {
   ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
   ; CHECK-NEXT:    bl      f_v4i32
   call i32 @f_v4i32(<4 x i32> <i32 50332416, i32 50332416, i32 50332416, i32 50332416>)
+  ; CHECK:         movi    v[[REG:[0-9]+]].8h, #0x2, lsl #8
+  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
+  ; CHECK-NEXT:    bl      f_v2i64
+  call i64 @f_v2i64(<2 x i64> <i64 144117387132666368, i64 144117387132666368>)
 
   ret void
 }
@@ -593,6 +637,9 @@ define void @modimm_t7_call() {
   ; CHECK-NEXT:    rev64   v{{[0-9]+}}.2s, v[[REG1]].2s
   ; CHECK-NEXT:    bl      f_v2i32
   call i32 @f_v2i32(<2 x i32> <i32 1791, i32 1791>)
+  ; CHECK:         movi    v{{[0-9]+}}.2s, #0x5, msl #8
+  ; CHECK-NEXT:    bl      f_v1i64
+  call i64 @f_v1i64(<1 x i64> <i64 6592774800895>)
   ; CHECK:         movi    v[[REG1:[0-9]+]].4s, #0x5, msl #8
   ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].16b, v[[REG1]].16b
   ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
@@ -608,6 +655,10 @@ define void @modimm_t7_call() {
   ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
   ; CHECK-NEXT:    bl      f_v4i32
   call i32 @f_v4i32(<4 x i32> <i32 1023, i32 1023, i32 1023, i32 1023>)
+  ; CHECK:         movi    v[[REG:[0-9]+]].4s, #0x2, msl #8
+  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
+  ; CHECK-NEXT:    bl      f_v2i64
+  call i64 @f_v2i64(<2 x i64> <i64 3294239916799, i64 3294239916799>)
 
   ret void
 }
@@ -626,6 +677,9 @@ define void @modimm_t8_call() {
   ; CHECK-NEXT:    rev64   v{{[0-9]+}}.2s, v[[REG1]].2s
   ; CHECK-NEXT:    bl      f_v2i32
   call i32 @f_v2i32(<2 x i32> <i32 458751, i32 458751>)
+  ; CHECK:         movi    v{{[0-9]+}}.2s, #0x5, msl #16
+  ; CHECK-NEXT:    bl      f_v1i64
+  call i64 @f_v1i64(<1 x i64> <i64 1688845565689855>)
   ; CHECK:         movi    v[[REG1:[0-9]+]].4s, #0x5, msl #16
   ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].16b, v[[REG1]].16b
   ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
@@ -641,6 +695,10 @@ define void @modimm_t8_call() {
   ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
   ; CHECK-NEXT:    bl      f_v4i32
   call i32 @f_v4i32(<4 x i32> <i32 262143, i32 262143, i32 262143, i32 262143>)
+  ; CHECK:         movi    v[[REG:[0-9]+]].4s, #0x2, msl #16
+  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
+  ; CHECK-NEXT:    bl      f_v2i64
+  call i64 @f_v2i64(<2 x i64> <i64 844420635361279, i64 844420635361279>)
 
   ret void
 }
@@ -725,6 +783,9 @@ define void @modimm_t11_call() {
   ; CHECK-NEXT:    rev64   v{{[0-9]+}}.2s, v[[REG1]].2s
   ; CHECK-NEXT:    bl      f_v2i32
   call i32 @f_v2i32(<2 x i32> <i32 1080033280, i32 1080033280>)
+  ; CHECK:         fmov    v{{[0-9]+}}.2s, #0.39062500
+  ; CHECK-NEXT:    bl      f_v1i64
+  call i64 @f_v1i64(<1 x i64> <i64 4523865826746957824>)
   ; CHECK:         fmov    v[[REG1:[0-9]+]].4s, #3.25000000
   ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].16b, v[[REG1]].16b
   ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
@@ -740,6 +801,10 @@ define void @modimm_t11_call() {
   ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
   ; CHECK-NEXT:    bl      f_v4i32
   call i32 @f_v4i32(<4 x i32> <i32 1076887552, i32 1076887552, i32 1076887552, i32 1076887552>)
+  ; CHECK:         fmov    v[[REG:[0-9]+]].4s, #2.5000000
+  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
+  ; CHECK-NEXT:    bl      f_v2i64
+  call i64 @f_v2i64(<2 x i64> <i64 4620693218757967872, i64 4620693218757967872>)
 
   ret void
 }