; CHECK-LABEL: test_varargs_stackalign:
; CHECK-DARWINPCS: stp {{w[0-9]+}}, {{w[0-9]+}}, [sp, #16]
- call void(...)* @callee([3 x float] undef, [2 x float] [float 1.0, float 2.0])
+ call void(...) @callee([3 x float] undef, [2 x float] [float 1.0, float 2.0])
ret void
}
%val = extractvalue [2 x <16 x i8>] %in, 0
ret <16 x i8> %val
}
+
+define half @test_f16_blocked([7 x double], [2 x half] %in) {
+; CHECK-LABEL: test_f16_blocked:
+; CHECK: ldr h0, [sp]
+ %val = extractvalue [2 x half] %in, 0
+ ret half %val
+}