[AArch64] Don't assert when combining (v3f32 select (setcc f64)).

[oota-llvm.git] / test / CodeGen / AArch64 / argument-blocks.ll

diff --git a/test/CodeGen/AArch64/argument-blocks.ll b/test/CodeGen/AArch64/argument-blocks.ll
index 9204da8d7ebefd90e970c3868223b0a0934b96df..3169abc2dcb3a7f0e009b16f68ed06f1bc60b7e1 100644 (file)
--- a/test/CodeGen/AArch64/argument-blocks.ll
+++ b/test/CodeGen/AArch64/argument-blocks.ll
@@ -64,7 +64,7 @@ define void @test_varargs_stackalign() {
 ; CHECK-LABEL: test_varargs_stackalign:
 ; CHECK-DARWINPCS: stp {{w[0-9]+}}, {{w[0-9]+}}, [sp, #16]
 
-  call void(...)* @callee([3 x float] undef, [2 x float] [float 1.0, float 2.0])
+  call void(...) @callee([3 x float] undef, [2 x float] [float 1.0, float 2.0])
   ret void
 }
 
@@ -188,3 +188,10 @@ define <16 x i8> @test_v16i8_blocked([7 x double], [2 x <16 x i8>] %in) {
   %val = extractvalue [2 x <16 x i8>] %in, 0
   ret <16 x i8> %val
 }
+
+define half @test_f16_blocked([7 x double], [2 x half] %in) {
+; CHECK-LABEL: test_f16_blocked:
+; CHECK: ldr h0, [sp]
+  %val = extractvalue [2 x half] %in, 0
+  ret half %val
+}