[FastISel][AArch64] Fix shift-immediate emission for "zero" shifts.

[oota-llvm.git] / test / CodeGen / AArch64 / arm64-ands-bad-peephole.ll

diff --git a/test/CodeGen/AArch64/arm64-ands-bad-peephole.ll b/test/CodeGen/AArch64/arm64-ands-bad-peephole.ll
index cf6235570a452a0fcc9ba53e5bbcc3deabf82d15..38661a5f38f30a0ca8162a6959fbb1905240cd69 100644 (file)
--- a/test/CodeGen/AArch64/arm64-ands-bad-peephole.ll
+++ b/test/CodeGen/AArch64/arm64-ands-bad-peephole.ll
@@ -1,4 +1,4 @@
-; RUN: llc %s -o - | FileCheck %s
+; RUN: llc %s -o - -aarch64-atomic-cfg-tidy=0 | FileCheck %s
 ; Check that ANDS (tst) is not merged with ADD when the immediate
 ; is not 0.
 ; <rdar://problem/16693089>