merge vector stores into wider vector stores and fix AArch64 misaligned access TLI...

[oota-llvm.git] / test / CodeGen / AArch64 / arm64-const-addr.ll

diff --git a/test/CodeGen/AArch64/arm64-const-addr.ll b/test/CodeGen/AArch64/arm64-const-addr.ll
index c55a9226cc7adc59edff8bcdff1ae819f413e7a9..ffc153344d3aa517dd3d690ccd8242e1806c1043 100644 (file)
--- a/test/CodeGen/AArch64/arm64-const-addr.ll
+++ b/test/CodeGen/AArch64/arm64-const-addr.ll
@@ -10,13 +10,13 @@ define i32 @test1() nounwind {
 ; CHECK-NEXT:   ldp w9, w10, [x8, #4]
 ; CHECK:        ldr w8, [x8, #12]
   %at = inttoptr i64 68141056 to %T*
-  %o1 = getelementptr %T* %at, i32 0, i32 1
-  %t1 = load i32* %o1
-  %o2 = getelementptr %T* %at, i32 0, i32 2
-  %t2 = load i32* %o2
+  %o1 = getelementptr %T, %T* %at, i32 0, i32 1
+  %t1 = load i32, i32* %o1
+  %o2 = getelementptr %T, %T* %at, i32 0, i32 2
+  %t2 = load i32, i32* %o2
   %a1 = add i32 %t1, %t2
-  %o3 = getelementptr %T* %at, i32 0, i32 3
-  %t3 = load i32* %o3
+  %o3 = getelementptr %T, %T* %at, i32 0, i32 3
+  %t3 = load i32, i32* %o3
   %a2 = add i32 %a1, %t3
   ret i32 %a2
 }