[AArch64][FastISel] Fix integer extend optimization.

[oota-llvm.git] / test / CodeGen / AArch64 / arm64-scvt.ll

diff --git a/test/CodeGen/AArch64/arm64-scvt.ll b/test/CodeGen/AArch64/arm64-scvt.ll
index d3b4ea48043fff4ed279c3361d20eabe712dd0a2..fc64d7bfda683d4260b0c4767c324a6a24cd2b85 100644 (file)
--- a/test/CodeGen/AArch64/arm64-scvt.ll
+++ b/test/CodeGen/AArch64/arm64-scvt.ll
@@ -7,7 +7,7 @@ entry:
 ; CHECK-LABEL: t1:
 ; CHECK: ldr s0, [x0]
 ; CHECK: scvtf s0, s0
-  %tmp1 = load i32* %src, align 4
+  %tmp1 = load i32, i32* %src, align 4
   %tmp2 = sitofp i32 %tmp1 to float
   ret float %tmp2
 }
@@ -17,7 +17,7 @@ entry:
 ; CHECK-LABEL: t2:
 ; CHECK: ldr s0, [x0]
 ; CHECK: ucvtf s0, s0
-  %tmp1 = load i32* %src, align 4
+  %tmp1 = load i32, i32* %src, align 4
   %tmp2 = uitofp i32 %tmp1 to float
   ret float %tmp2
 }
@@ -27,7 +27,7 @@ entry:
 ; CHECK-LABEL: t3:
 ; CHECK: ldr d0, [x0]
 ; CHECK: scvtf d0, d0
-  %tmp1 = load i64* %src, align 4
+  %tmp1 = load i64, i64* %src, align 4
   %tmp2 = sitofp i64 %tmp1 to double
   ret double %tmp2
 }
@@ -37,7 +37,7 @@ entry:
 ; CHECK-LABEL: t4:
 ; CHECK: ldr d0, [x0]
 ; CHECK: ucvtf d0, d0
-  %tmp1 = load i64* %src, align 4
+  %tmp1 = load i64, i64* %src, align 4
   %tmp2 = uitofp i64 %tmp1 to double
   ret double %tmp2
 }
@@ -48,7 +48,7 @@ entry:
 ; CHECK-LABEL: t5:
 ; CHECK: ldr [[REG:w[0-9]+]], [x0]
 ; CHECK: scvtf d0, [[REG]]
-  %tmp1 = load i32* %src, align 4
+  %tmp1 = load i32, i32* %src, align 4
   %tmp2 = sitofp i32 %tmp1 to double
   ret double %tmp2
 }
@@ -76,7 +76,7 @@ define float @fct1(i8* nocapture %sp0) {
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i8, i8* %sp0, i64 1
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = uitofp i8 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -89,7 +89,7 @@ define float @fct2(i16* nocapture %sp0) {
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i16, i16* %sp0, i64 1
-  %pix_sp0.0.copyload = load i16* %addr, align 1
+  %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = uitofp i16 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -102,7 +102,7 @@ define float @fct3(i32* nocapture %sp0) {
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i32, i32* %sp0, i64 1
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = uitofp i32 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -116,7 +116,7 @@ define float @fct4(i64* nocapture %sp0) {
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i64, i64* %sp0, i64 1
-  %pix_sp0.0.copyload = load i64* %addr, align 1
+  %pix_sp0.0.copyload = load i64, i64* %addr, align 1
   %val = uitofp i64 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -130,7 +130,7 @@ define float @fct5(i8* nocapture %sp0, i64 %offset) {
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i8, i8* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = uitofp i8 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -143,7 +143,7 @@ define float @fct6(i16* nocapture %sp0, i64 %offset) {
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i16, i16* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i16* %addr, align 1
+  %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = uitofp i16 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -156,7 +156,7 @@ define float @fct7(i32* nocapture %sp0, i64 %offset) {
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i32, i32* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = uitofp i32 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -170,7 +170,7 @@ define float @fct8(i64* nocapture %sp0, i64 %offset) {
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i64, i64* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i64* %addr, align 1
+  %pix_sp0.0.copyload = load i64, i64* %addr, align 1
   %val = uitofp i64 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -185,7 +185,7 @@ define double @fct9(i8* nocapture %sp0) {
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i8, i8* %sp0, i64 1
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = uitofp i8 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -198,7 +198,7 @@ define double @fct10(i16* nocapture %sp0) {
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i16, i16* %sp0, i64 1
-  %pix_sp0.0.copyload = load i16* %addr, align 1
+  %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = uitofp i16 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -211,7 +211,7 @@ define double @fct11(i32* nocapture %sp0) {
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i32, i32* %sp0, i64 1
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = uitofp i32 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -224,7 +224,7 @@ define double @fct12(i64* nocapture %sp0) {
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i64, i64* %sp0, i64 1
-  %pix_sp0.0.copyload = load i64* %addr, align 1
+  %pix_sp0.0.copyload = load i64, i64* %addr, align 1
   %val = uitofp i64 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -238,7 +238,7 @@ define double @fct13(i8* nocapture %sp0, i64 %offset) {
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i8, i8* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = uitofp i8 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -251,7 +251,7 @@ define double @fct14(i16* nocapture %sp0, i64 %offset) {
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i16, i16* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i16* %addr, align 1
+  %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = uitofp i16 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -264,7 +264,7 @@ define double @fct15(i32* nocapture %sp0, i64 %offset) {
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i32, i32* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = uitofp i32 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -277,7 +277,7 @@ define double @fct16(i64* nocapture %sp0, i64 %offset) {
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i64, i64* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i64* %addr, align 1
+  %pix_sp0.0.copyload = load i64, i64* %addr, align 1
   %val = uitofp i64 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -293,7 +293,7 @@ entry:
   %bitcast = ptrtoint i8* %sp0 to i64
   %add = add i64 %bitcast, -1
   %addr = inttoptr i64 %add to i8*
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = uitofp i8 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -307,7 +307,7 @@ define float @fct18(i16* nocapture %sp0) {
   %bitcast = ptrtoint i16* %sp0 to i64
   %add = add i64 %bitcast, 1
   %addr = inttoptr i64 %add to i16*
-  %pix_sp0.0.copyload = load i16* %addr, align 1
+  %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = uitofp i16 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -321,7 +321,7 @@ define float @fct19(i32* nocapture %sp0) {
   %bitcast = ptrtoint i32* %sp0 to i64
   %add = add i64 %bitcast, 1
   %addr = inttoptr i64 %add to i32*
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = uitofp i32 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -336,7 +336,7 @@ define float @fct20(i64* nocapture %sp0) {
   %bitcast = ptrtoint i64* %sp0 to i64
   %add = add i64 %bitcast, 1
   %addr = inttoptr i64 %add to i64*
-  %pix_sp0.0.copyload = load i64* %addr, align 1
+  %pix_sp0.0.copyload = load i64, i64* %addr, align 1
   %val = uitofp i64 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -353,7 +353,7 @@ entry:
   %bitcast = ptrtoint i8* %sp0 to i64
   %add = add i64 %bitcast, -1
   %addr = inttoptr i64 %add to i8*
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = uitofp i8 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -367,7 +367,7 @@ define double @fct22(i16* nocapture %sp0) {
   %bitcast = ptrtoint i16* %sp0 to i64
   %add = add i64 %bitcast, 1
   %addr = inttoptr i64 %add to i16*
-  %pix_sp0.0.copyload = load i16* %addr, align 1
+  %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = uitofp i16 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -381,7 +381,7 @@ define double @fct23(i32* nocapture %sp0) {
   %bitcast = ptrtoint i32* %sp0 to i64
   %add = add i64 %bitcast, 1
   %addr = inttoptr i64 %add to i32*
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = uitofp i32 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -395,7 +395,7 @@ define double @fct24(i64* nocapture %sp0) {
   %bitcast = ptrtoint i64* %sp0 to i64
   %add = add i64 %bitcast, 1
   %addr = inttoptr i64 %add to i64*
-  %pix_sp0.0.copyload = load i64* %addr, align 1
+  %pix_sp0.0.copyload = load i64, i64* %addr, align 1
   %val = uitofp i64 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -416,7 +416,7 @@ define float @sfct1(i8* nocapture %sp0) {
 ; CHECK-A57-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i8, i8* %sp0, i64 1
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = sitofp i8 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -430,7 +430,7 @@ define float @sfct2(i16* nocapture %sp0) {
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i16, i16* %sp0, i64 1
-  %pix_sp0.0.copyload = load i16* %addr, align 1
+  %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = sitofp i16 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -443,7 +443,7 @@ define float @sfct3(i32* nocapture %sp0) {
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i32, i32* %sp0, i64 1
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = sitofp i32 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -457,7 +457,7 @@ define float @sfct4(i64* nocapture %sp0) {
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i64, i64* %sp0, i64 1
-  %pix_sp0.0.copyload = load i64* %addr, align 1
+  %pix_sp0.0.copyload = load i64, i64* %addr, align 1
   %val = sitofp i64 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -477,7 +477,7 @@ define float @sfct5(i8* nocapture %sp0, i64 %offset) {
 ; CHECK-A57-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i8, i8* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = sitofp i8 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -491,7 +491,7 @@ define float @sfct6(i16* nocapture %sp0, i64 %offset) {
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i16, i16* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i16* %addr, align 1
+  %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = sitofp i16 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -504,7 +504,7 @@ define float @sfct7(i32* nocapture %sp0, i64 %offset) {
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i32, i32* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = sitofp i32 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -518,7 +518,7 @@ define float @sfct8(i64* nocapture %sp0, i64 %offset) {
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i64, i64* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i64* %addr, align 1
+  %pix_sp0.0.copyload = load i64, i64* %addr, align 1
   %val = sitofp i64 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -532,7 +532,7 @@ define double @sfct9(i8* nocapture %sp0) {
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i8, i8* %sp0, i64 1
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = sitofp i8 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -551,7 +551,7 @@ define double @sfct10(i16* nocapture %sp0) {
 ; CHECK-A57-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i16, i16* %sp0, i64 1
-  %pix_sp0.0.copyload = load i16* %addr, align 1
+  %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = sitofp i16 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -565,7 +565,7 @@ define double @sfct11(i32* nocapture %sp0) {
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i32, i32* %sp0, i64 1
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = sitofp i32 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -578,7 +578,7 @@ define double @sfct12(i64* nocapture %sp0) {
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i64, i64* %sp0, i64 1
-  %pix_sp0.0.copyload = load i64* %addr, align 1
+  %pix_sp0.0.copyload = load i64, i64* %addr, align 1
   %val = sitofp i64 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -592,7 +592,7 @@ define double @sfct13(i8* nocapture %sp0, i64 %offset) {
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i8, i8* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = sitofp i8 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -611,7 +611,7 @@ define double @sfct14(i16* nocapture %sp0, i64 %offset) {
 ; CHECK-A57-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i16, i16* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i16* %addr, align 1
+  %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = sitofp i16 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -625,7 +625,7 @@ define double @sfct15(i32* nocapture %sp0, i64 %offset) {
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i32, i32* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = sitofp i32 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -638,7 +638,7 @@ define double @sfct16(i64* nocapture %sp0, i64 %offset) {
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i64, i64* %sp0, i64 %offset
-  %pix_sp0.0.copyload = load i64* %addr, align 1
+  %pix_sp0.0.copyload = load i64, i64* %addr, align 1
   %val = sitofp i64 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -660,7 +660,7 @@ entry:
   %bitcast = ptrtoint i8* %sp0 to i64
   %add = add i64 %bitcast, -1
   %addr = inttoptr i64 %add to i8*
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = sitofp i8 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -675,7 +675,7 @@ define float @sfct18(i16* nocapture %sp0) {
   %bitcast = ptrtoint i16* %sp0 to i64
   %add = add i64 %bitcast, 1
   %addr = inttoptr i64 %add to i16*
-  %pix_sp0.0.copyload = load i16* %addr, align 1
+  %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = sitofp i16 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -689,7 +689,7 @@ define float @sfct19(i32* nocapture %sp0) {
   %bitcast = ptrtoint i32* %sp0 to i64
   %add = add i64 %bitcast, 1
   %addr = inttoptr i64 %add to i32*
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = sitofp i32 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -704,7 +704,7 @@ define float @sfct20(i64* nocapture %sp0) {
   %bitcast = ptrtoint i64* %sp0 to i64
   %add = add i64 %bitcast, 1
   %addr = inttoptr i64 %add to i64*
-  %pix_sp0.0.copyload = load i64* %addr, align 1
+  %pix_sp0.0.copyload = load i64, i64* %addr, align 1
   %val = sitofp i64 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -721,7 +721,7 @@ entry:
   %bitcast = ptrtoint i8* %sp0 to i64
   %add = add i64 %bitcast, -1
   %addr = inttoptr i64 %add to i8*
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = sitofp i8 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -741,7 +741,7 @@ define double @sfct22(i16* nocapture %sp0) {
   %bitcast = ptrtoint i16* %sp0 to i64
   %add = add i64 %bitcast, 1
   %addr = inttoptr i64 %add to i16*
-  %pix_sp0.0.copyload = load i16* %addr, align 1
+  %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = sitofp i16 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -756,7 +756,7 @@ define double @sfct23(i32* nocapture %sp0) {
   %bitcast = ptrtoint i32* %sp0 to i64
   %add = add i64 %bitcast, 1
   %addr = inttoptr i64 %add to i32*
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = sitofp i32 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -770,7 +770,7 @@ define double @sfct24(i64* nocapture %sp0) {
   %bitcast = ptrtoint i64* %sp0 to i64
   %add = add i64 %bitcast, 1
   %addr = inttoptr i64 %add to i64*
-  %pix_sp0.0.copyload = load i64* %addr, align 1
+  %pix_sp0.0.copyload = load i64, i64* %addr, align 1
   %val = sitofp i64 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
@@ -787,7 +787,7 @@ entry:
   %bitcast = ptrtoint i8* %sp0 to i64
   %add = add i64 %bitcast, -1
   %addr = inttoptr i64 %add to i8*
-  %pix_sp0.0.copyload = load i8* %addr, align 1
+  %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = sitofp i8 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
@@ -800,7 +800,7 @@ define double @codesize_sfct11(i32* nocapture %sp0) minsize {
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i32, i32* %sp0, i64 1
-  %pix_sp0.0.copyload = load i32* %addr, align 1
+  %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = sitofp i32 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i