[Hexagon] Use A2_tfrsi for constant pool and jump table addresses

[oota-llvm.git] / test / CodeGen / AArch64 / arm64-vhsub.ll

diff --git a/test/CodeGen/AArch64/arm64-vhsub.ll b/test/CodeGen/AArch64/arm64-vhsub.ll
index 13bfda3899e5c54b87d3531bcc39db975ecf6be7..e50fd3d358965b965de97239b4d72a3d66932451 100644 (file)
--- a/test/CodeGen/AArch64/arm64-vhsub.ll
+++ b/test/CodeGen/AArch64/arm64-vhsub.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @shsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: shsub8b:
 ;CHECK: shsub.8b
-       %tmp1 = load <8 x i8>* %A
-       %tmp2 = load <8 x i8>* %B
+       %tmp1 = load <8 x i8>, <8 x i8>* %A
+       %tmp2 = load <8 x i8>, <8 x i8>* %B
        %tmp3 = call <8 x i8> @llvm.aarch64.neon.shsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
        ret <8 x i8> %tmp3
 }
@@ -12,8 +12,8 @@ define <8 x i8> @shsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <16 x i8> @shsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: shsub16b:
 ;CHECK: shsub.16b
-       %tmp1 = load <16 x i8>* %A
-       %tmp2 = load <16 x i8>* %B
+       %tmp1 = load <16 x i8>, <16 x i8>* %A
+       %tmp2 = load <16 x i8>, <16 x i8>* %B
        %tmp3 = call <16 x i8> @llvm.aarch64.neon.shsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
        ret <16 x i8> %tmp3
 }
@@ -21,8 +21,8 @@ define <16 x i8> @shsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <4 x i16> @shsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: shsub4h:
 ;CHECK: shsub.4h
-       %tmp1 = load <4 x i16>* %A
-       %tmp2 = load <4 x i16>* %B
+       %tmp1 = load <4 x i16>, <4 x i16>* %A
+       %tmp2 = load <4 x i16>, <4 x i16>* %B
        %tmp3 = call <4 x i16> @llvm.aarch64.neon.shsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
        ret <4 x i16> %tmp3
 }
@@ -30,8 +30,8 @@ define <4 x i16> @shsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <8 x i16> @shsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: shsub8h:
 ;CHECK: shsub.8h
-       %tmp1 = load <8 x i16>* %A
-       %tmp2 = load <8 x i16>* %B
+       %tmp1 = load <8 x i16>, <8 x i16>* %A
+       %tmp2 = load <8 x i16>, <8 x i16>* %B
        %tmp3 = call <8 x i16> @llvm.aarch64.neon.shsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
        ret <8 x i16> %tmp3
 }
@@ -39,8 +39,8 @@ define <8 x i16> @shsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <2 x i32> @shsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: shsub2s:
 ;CHECK: shsub.2s
-       %tmp1 = load <2 x i32>* %A
-       %tmp2 = load <2 x i32>* %B
+       %tmp1 = load <2 x i32>, <2 x i32>* %A
+       %tmp2 = load <2 x i32>, <2 x i32>* %B
        %tmp3 = call <2 x i32> @llvm.aarch64.neon.shsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
        ret <2 x i32> %tmp3
 }
@@ -48,8 +48,8 @@ define <2 x i32> @shsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <4 x i32> @shsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: shsub4s:
 ;CHECK: shsub.4s
-       %tmp1 = load <4 x i32>* %A
-       %tmp2 = load <4 x i32>* %B
+       %tmp1 = load <4 x i32>, <4 x i32>* %A
+       %tmp2 = load <4 x i32>, <4 x i32>* %B
        %tmp3 = call <4 x i32> @llvm.aarch64.neon.shsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
        ret <4 x i32> %tmp3
 }
@@ -57,8 +57,8 @@ define <4 x i32> @shsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <8 x i8> @uhsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: uhsub8b:
 ;CHECK: uhsub.8b
-       %tmp1 = load <8 x i8>* %A
-       %tmp2 = load <8 x i8>* %B
+       %tmp1 = load <8 x i8>, <8 x i8>* %A
+       %tmp2 = load <8 x i8>, <8 x i8>* %B
        %tmp3 = call <8 x i8> @llvm.aarch64.neon.uhsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
        ret <8 x i8> %tmp3
 }
@@ -66,8 +66,8 @@ define <8 x i8> @uhsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <16 x i8> @uhsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: uhsub16b:
 ;CHECK: uhsub.16b
-       %tmp1 = load <16 x i8>* %A
-       %tmp2 = load <16 x i8>* %B
+       %tmp1 = load <16 x i8>, <16 x i8>* %A
+       %tmp2 = load <16 x i8>, <16 x i8>* %B
        %tmp3 = call <16 x i8> @llvm.aarch64.neon.uhsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
        ret <16 x i8> %tmp3
 }
@@ -75,8 +75,8 @@ define <16 x i8> @uhsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <4 x i16> @uhsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: uhsub4h:
 ;CHECK: uhsub.4h
-       %tmp1 = load <4 x i16>* %A
-       %tmp2 = load <4 x i16>* %B
+       %tmp1 = load <4 x i16>, <4 x i16>* %A
+       %tmp2 = load <4 x i16>, <4 x i16>* %B
        %tmp3 = call <4 x i16> @llvm.aarch64.neon.uhsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
        ret <4 x i16> %tmp3
 }
@@ -84,8 +84,8 @@ define <4 x i16> @uhsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <8 x i16> @uhsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: uhsub8h:
 ;CHECK: uhsub.8h
-       %tmp1 = load <8 x i16>* %A
-       %tmp2 = load <8 x i16>* %B
+       %tmp1 = load <8 x i16>, <8 x i16>* %A
+       %tmp2 = load <8 x i16>, <8 x i16>* %B
        %tmp3 = call <8 x i16> @llvm.aarch64.neon.uhsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
        ret <8 x i16> %tmp3
 }
@@ -93,8 +93,8 @@ define <8 x i16> @uhsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <2 x i32> @uhsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: uhsub2s:
 ;CHECK: uhsub.2s
-       %tmp1 = load <2 x i32>* %A
-       %tmp2 = load <2 x i32>* %B
+       %tmp1 = load <2 x i32>, <2 x i32>* %A
+       %tmp2 = load <2 x i32>, <2 x i32>* %B
        %tmp3 = call <2 x i32> @llvm.aarch64.neon.uhsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
        ret <2 x i32> %tmp3
 }
@@ -102,8 +102,8 @@ define <2 x i32> @uhsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <4 x i32> @uhsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: uhsub4s:
 ;CHECK: uhsub.4s
-       %tmp1 = load <4 x i32>* %A
-       %tmp2 = load <4 x i32>* %B
+       %tmp1 = load <4 x i32>, <4 x i32>* %A
+       %tmp2 = load <4 x i32>, <4 x i32>* %B
        %tmp3 = call <4 x i32> @llvm.aarch64.neon.uhsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
        ret <4 x i32> %tmp3
 }