[Hexagon] Use A2_tfrsi for constant pool and jump table addresses

[oota-llvm.git] / test / CodeGen / AArch64 / arm64-vqsub.ll

diff --git a/test/CodeGen/AArch64/arm64-vqsub.ll b/test/CodeGen/AArch64/arm64-vqsub.ll
index dde3ac3478e45cf1bb78d3b888c1729fc7159614..4fc588d689f9aed40f8cf00e7b6efa8fb0cbf91c 100644 (file)
--- a/test/CodeGen/AArch64/arm64-vqsub.ll
+++ b/test/CodeGen/AArch64/arm64-vqsub.ll
@@ -3,8 +3,8 @@
 define <8 x i8> @sqsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: sqsub8b:
 ;CHECK: sqsub.8b
-       %tmp1 = load <8 x i8>* %A
-       %tmp2 = load <8 x i8>* %B
+       %tmp1 = load <8 x i8>, <8 x i8>* %A
+       %tmp2 = load <8 x i8>, <8 x i8>* %B
        %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
        ret <8 x i8> %tmp3
 }
@@ -12,8 +12,8 @@ define <8 x i8> @sqsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @sqsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: sqsub4h:
 ;CHECK: sqsub.4h
-       %tmp1 = load <4 x i16>* %A
-       %tmp2 = load <4 x i16>* %B
+       %tmp1 = load <4 x i16>, <4 x i16>* %A
+       %tmp2 = load <4 x i16>, <4 x i16>* %B
        %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
        ret <4 x i16> %tmp3
 }
@@ -21,8 +21,8 @@ define <4 x i16> @sqsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @sqsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: sqsub2s:
 ;CHECK: sqsub.2s
-       %tmp1 = load <2 x i32>* %A
-       %tmp2 = load <2 x i32>* %B
+       %tmp1 = load <2 x i32>, <2 x i32>* %A
+       %tmp2 = load <2 x i32>, <2 x i32>* %B
        %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
        ret <2 x i32> %tmp3
 }
@@ -30,8 +30,8 @@ define <2 x i32> @sqsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <8 x i8> @uqsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: uqsub8b:
 ;CHECK: uqsub.8b
-       %tmp1 = load <8 x i8>* %A
-       %tmp2 = load <8 x i8>* %B
+       %tmp1 = load <8 x i8>, <8 x i8>* %A
+       %tmp2 = load <8 x i8>, <8 x i8>* %B
        %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
        ret <8 x i8> %tmp3
 }
@@ -39,8 +39,8 @@ define <8 x i8> @uqsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 define <4 x i16> @uqsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK-LABEL: uqsub4h:
 ;CHECK: uqsub.4h
-       %tmp1 = load <4 x i16>* %A
-       %tmp2 = load <4 x i16>* %B
+       %tmp1 = load <4 x i16>, <4 x i16>* %A
+       %tmp2 = load <4 x i16>, <4 x i16>* %B
        %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
        ret <4 x i16> %tmp3
 }
@@ -48,8 +48,8 @@ define <4 x i16> @uqsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 define <2 x i32> @uqsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK-LABEL: uqsub2s:
 ;CHECK: uqsub.2s
-       %tmp1 = load <2 x i32>* %A
-       %tmp2 = load <2 x i32>* %B
+       %tmp1 = load <2 x i32>, <2 x i32>* %A
+       %tmp2 = load <2 x i32>, <2 x i32>* %B
        %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
        ret <2 x i32> %tmp3
 }
@@ -57,8 +57,8 @@ define <2 x i32> @uqsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 define <16 x i8> @sqsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: sqsub16b:
 ;CHECK: sqsub.16b
-       %tmp1 = load <16 x i8>* %A
-       %tmp2 = load <16 x i8>* %B
+       %tmp1 = load <16 x i8>, <16 x i8>* %A
+       %tmp2 = load <16 x i8>, <16 x i8>* %B
        %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
        ret <16 x i8> %tmp3
 }
@@ -66,8 +66,8 @@ define <16 x i8> @sqsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @sqsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: sqsub8h:
 ;CHECK: sqsub.8h
-       %tmp1 = load <8 x i16>* %A
-       %tmp2 = load <8 x i16>* %B
+       %tmp1 = load <8 x i16>, <8 x i16>* %A
+       %tmp2 = load <8 x i16>, <8 x i16>* %B
        %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
        ret <8 x i16> %tmp3
 }
@@ -75,8 +75,8 @@ define <8 x i16> @sqsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @sqsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: sqsub4s:
 ;CHECK: sqsub.4s
-       %tmp1 = load <4 x i32>* %A
-       %tmp2 = load <4 x i32>* %B
+       %tmp1 = load <4 x i32>, <4 x i32>* %A
+       %tmp2 = load <4 x i32>, <4 x i32>* %B
        %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
        ret <4 x i32> %tmp3
 }
@@ -84,8 +84,8 @@ define <4 x i32> @sqsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @sqsub2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: sqsub2d:
 ;CHECK: sqsub.2d
-       %tmp1 = load <2 x i64>* %A
-       %tmp2 = load <2 x i64>* %B
+       %tmp1 = load <2 x i64>, <2 x i64>* %A
+       %tmp2 = load <2 x i64>, <2 x i64>* %B
        %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
        ret <2 x i64> %tmp3
 }
@@ -93,8 +93,8 @@ define <2 x i64> @sqsub2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 define <16 x i8> @uqsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK-LABEL: uqsub16b:
 ;CHECK: uqsub.16b
-       %tmp1 = load <16 x i8>* %A
-       %tmp2 = load <16 x i8>* %B
+       %tmp1 = load <16 x i8>, <16 x i8>* %A
+       %tmp2 = load <16 x i8>, <16 x i8>* %B
        %tmp3 = call <16 x i8> @llvm.aarch64.neon.uqsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
        ret <16 x i8> %tmp3
 }
@@ -102,8 +102,8 @@ define <16 x i8> @uqsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 define <8 x i16> @uqsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK-LABEL: uqsub8h:
 ;CHECK: uqsub.8h
-       %tmp1 = load <8 x i16>* %A
-       %tmp2 = load <8 x i16>* %B
+       %tmp1 = load <8 x i16>, <8 x i16>* %A
+       %tmp2 = load <8 x i16>, <8 x i16>* %B
        %tmp3 = call <8 x i16> @llvm.aarch64.neon.uqsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
        ret <8 x i16> %tmp3
 }
@@ -111,8 +111,8 @@ define <8 x i16> @uqsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i32> @uqsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK-LABEL: uqsub4s:
 ;CHECK: uqsub.4s
-       %tmp1 = load <4 x i32>* %A
-       %tmp2 = load <4 x i32>* %B
+       %tmp1 = load <4 x i32>, <4 x i32>* %A
+       %tmp2 = load <4 x i32>, <4 x i32>* %B
        %tmp3 = call <4 x i32> @llvm.aarch64.neon.uqsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
        ret <4 x i32> %tmp3
 }
@@ -120,8 +120,8 @@ define <4 x i32> @uqsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 define <2 x i64> @uqsub2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ;CHECK-LABEL: uqsub2d:
 ;CHECK: uqsub.2d
-       %tmp1 = load <2 x i64>* %A
-       %tmp2 = load <2 x i64>* %B
+       %tmp1 = load <2 x i64>, <2 x i64>* %A
+       %tmp2 = load <2 x i64>, <2 x i64>* %B
        %tmp3 = call <2 x i64> @llvm.aarch64.neon.uqsub.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
        ret <2 x i64> %tmp3
 }