[AArch64] Fix sext/zext folding in address arithmetic.

[oota-llvm.git] / test / CodeGen / AArch64 / arm64-vshr.ll

diff --git a/test/CodeGen/AArch64/arm64-vshr.ll b/test/CodeGen/AArch64/arm64-vshr.ll
index 21eb579f25225503cada459e30d8719b8704e524..8d263f22c54e2d3460ecab6922688e8bfc7e9e22 100644 (file)
--- a/test/CodeGen/AArch64/arm64-vshr.ll
+++ b/test/CodeGen/AArch64/arm64-vshr.ll
@@ -10,8 +10,8 @@ entry:
   %b.addr = alloca <8 x i16>, align 16
   store <8 x i16> %a, <8 x i16>* %a.addr, align 16
   store <8 x i16> %b, <8 x i16>* %b.addr, align 16
-  %0 = load <8 x i16>* %a.addr, align 16
-  %1 = load <8 x i16>* %b.addr, align 16
+  %0 = load <8 x i16>, <8 x i16>* %a.addr, align 16
+  %1 = load <8 x i16>, <8 x i16>* %b.addr, align 16
   %shr = ashr <8 x i16> %0, %1
   ret <8 x i16> %shr
 }
@@ -25,8 +25,8 @@ entry:
   %b.addr = alloca <4 x i32>, align 32
   store <4 x i32> %a, <4 x i32>* %a.addr, align 32
   store <4 x i32> %b, <4 x i32>* %b.addr, align 32
-  %0 = load <4 x i32>* %a.addr, align 32
-  %1 = load <4 x i32>* %b.addr, align 32
+  %0 = load <4 x i32>, <4 x i32>* %a.addr, align 32
+  %1 = load <4 x i32>, <4 x i32>* %b.addr, align 32
   %shr = ashr <4 x i32> %0, %1
   ret <4 x i32> %shr
 }
@@ -40,8 +40,8 @@ entry:
   %b.addr = alloca <8 x i16>, align 16
   store <8 x i16> %a, <8 x i16>* %a.addr, align 16
   store <8 x i16> %b, <8 x i16>* %b.addr, align 16
-  %0 = load <8 x i16>* %a.addr, align 16
-  %1 = load <8 x i16>* %b.addr, align 16
+  %0 = load <8 x i16>, <8 x i16>* %a.addr, align 16
+  %1 = load <8 x i16>, <8 x i16>* %b.addr, align 16
   %shr = lshr <8 x i16> %0, %1
   ret <8 x i16> %shr
 }