[AArch64] Don't assert when combining (v3f32 select (setcc f64)).

[oota-llvm.git] / test / CodeGen / AArch64 / assertion-rc-mismatch.ll

diff --git a/test/CodeGen/AArch64/assertion-rc-mismatch.ll b/test/CodeGen/AArch64/assertion-rc-mismatch.ll
index bcf206ec9bed5d0393b3dfcb8ea7fcd0796b0a78..c216c448e11b51675ef0f61975dd653420a20e64 100644 (file)
--- a/test/CodeGen/AArch64/assertion-rc-mismatch.ll
+++ b/test/CodeGen/AArch64/assertion-rc-mismatch.ll
@@ -11,8 +11,8 @@ if:
   br label %end
 else:
   %tmp3 = call i8* @llvm.returnaddress(i32 0)
-  %ptr = getelementptr inbounds i8* %tmp3, i64 -16
-  %ld = load i8* %ptr, align 4
+  %ptr = getelementptr inbounds i8, i8* %tmp3, i64 -16
+  %ld = load i8, i8* %ptr, align 4
   %tmp2 = inttoptr i8 %ld to i8*
   br label %end
 end: