merge vector stores into wider vector stores and fix AArch64 misaligned access TLI...

[oota-llvm.git] / test / CodeGen / AArch64 / compare-branch.ll

diff --git a/test/CodeGen/AArch64/compare-branch.ll b/test/CodeGen/AArch64/compare-branch.ll
index 4213110497d3b8800058603c862e73b18a24c89d..4e0f69d195c2ef26ba419ab077c2ccb29ebe2224 100644 (file)
--- a/test/CodeGen/AArch64/compare-branch.ll
+++ b/test/CodeGen/AArch64/compare-branch.ll
@@ -1,30 +1,30 @@
-; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
+; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s
 
 @var32 = global i32 0
 @var64 = global i64 0
 
 define void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 
-  %val1 = load volatile i32* @var32
+  %val1 = load volatile i32, i32* @var32
   %tst1 = icmp eq i32 %val1, 0
   br i1 %tst1, label %end, label %test2
 ; CHECK: cbz {{w[0-9]+}}, .LBB
 
 test2:
-  %val2 = load volatile i32* @var32
+  %val2 = load volatile i32, i32* @var32
   %tst2 = icmp ne i32 %val2, 0
   br i1 %tst2, label %end, label %test3
 ; CHECK: cbnz {{w[0-9]+}}, .LBB
 
 test3:
-  %val3 = load volatile i64* @var64
+  %val3 = load volatile i64, i64* @var64
   %tst3 = icmp eq i64 %val3, 0
   br i1 %tst3, label %end, label %test4
 ; CHECK: cbz {{x[0-9]+}}, .LBB
 
 test4:
-  %val4 = load volatile i64* @var64
+  %val4 = load volatile i64, i64* @var64
   %tst4 = icmp ne i64 %val4, 0
   br i1 %tst4, label %end, label %test5
 ; CHECK: cbnz {{x[0-9]+}}, .LBB
@@ -35,4 +35,4 @@ test5:
 
 end:
   ret void
-}
\ No newline at end of file
+}