[AArch64] Fix sext/zext folding in address arithmetic.

[oota-llvm.git] / test / CodeGen / AArch64 / dp2.ll

diff --git a/test/CodeGen/AArch64/dp2.ll b/test/CodeGen/AArch64/dp2.ll
index 71b31696372ac3e9c0e5f3dd34cb358807d8df30..0cd2d7ed84a73122675d1ed0899a6e66ed7f4e92 100644 (file)
--- a/test/CodeGen/AArch64/dp2.ll
+++ b/test/CodeGen/AArch64/dp2.ll
@@ -7,8 +7,8 @@
 
 define void @rorv_i64() {
 ; CHECK-LABEL: rorv_i64:
-    %val0_tmp = load i64* @var64_0
-    %val1_tmp = load i64* @var64_1
+    %val0_tmp = load i64, i64* @var64_0
+    %val1_tmp = load i64, i64* @var64_1
     %val2_tmp = sub i64 64, %val1_tmp
     %val3_tmp = shl i64 %val0_tmp, %val2_tmp
     %val4_tmp = lshr i64 %val0_tmp, %val1_tmp
@@ -20,8 +20,8 @@ define void @rorv_i64() {
 
 define void @asrv_i64() {
 ; CHECK-LABEL: asrv_i64:
-    %val0_tmp = load i64* @var64_0
-    %val1_tmp = load i64* @var64_1
+    %val0_tmp = load i64, i64* @var64_0
+    %val1_tmp = load i64, i64* @var64_1
     %val4_tmp = ashr i64 %val0_tmp, %val1_tmp
 ; CHECK: {{asr|asrv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
     store volatile i64 %val4_tmp, i64* @var64_1
@@ -30,8 +30,8 @@ define void @asrv_i64() {
 
 define void @lsrv_i64() {
 ; CHECK-LABEL: lsrv_i64:
-    %val0_tmp = load i64* @var64_0
-    %val1_tmp = load i64* @var64_1
+    %val0_tmp = load i64, i64* @var64_0
+    %val1_tmp = load i64, i64* @var64_1
     %val4_tmp = lshr i64 %val0_tmp, %val1_tmp
 ; CHECK: {{lsr|lsrv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
     store volatile i64 %val4_tmp, i64* @var64_0
@@ -40,8 +40,8 @@ define void @lsrv_i64() {
 
 define void @lslv_i64() {
 ; CHECK-LABEL: lslv_i64:
-    %val0_tmp = load i64* @var64_0
-    %val1_tmp = load i64* @var64_1
+    %val0_tmp = load i64, i64* @var64_0
+    %val1_tmp = load i64, i64* @var64_1
     %val4_tmp = shl i64 %val0_tmp, %val1_tmp
 ; CHECK: {{lsl|lslv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
     store volatile i64 %val4_tmp, i64* @var64_1
@@ -50,8 +50,8 @@ define void @lslv_i64() {
 
 define void @udiv_i64() {
 ; CHECK-LABEL: udiv_i64:
-    %val0_tmp = load i64* @var64_0
-    %val1_tmp = load i64* @var64_1
+    %val0_tmp = load i64, i64* @var64_0
+    %val1_tmp = load i64, i64* @var64_1
     %val4_tmp = udiv i64 %val0_tmp, %val1_tmp
 ; CHECK: udiv  {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
     store volatile i64 %val4_tmp, i64* @var64_0
@@ -60,8 +60,8 @@ define void @udiv_i64() {
 
 define void @sdiv_i64() {
 ; CHECK-LABEL: sdiv_i64:
-    %val0_tmp = load i64* @var64_0
-    %val1_tmp = load i64* @var64_1
+    %val0_tmp = load i64, i64* @var64_0
+    %val1_tmp = load i64, i64* @var64_1
     %val4_tmp = sdiv i64 %val0_tmp, %val1_tmp
 ; CHECK: sdiv  {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
     store volatile i64 %val4_tmp, i64* @var64_1
@@ -71,8 +71,8 @@ define void @sdiv_i64() {
 
 define void @lsrv_i32() {
 ; CHECK-LABEL: lsrv_i32:
-    %val0_tmp = load i32* @var32_0
-    %val1_tmp = load i32* @var32_1
+    %val0_tmp = load i32, i32* @var32_0
+    %val1_tmp = load i32, i32* @var32_1
     %val2_tmp = add i32 1, %val1_tmp
     %val4_tmp = lshr i32 %val0_tmp, %val2_tmp
 ; CHECK: {{lsr|lsrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
@@ -82,8 +82,8 @@ define void @lsrv_i32() {
 
 define void @lslv_i32() {
 ; CHECK-LABEL: lslv_i32:
-    %val0_tmp = load i32* @var32_0
-    %val1_tmp = load i32* @var32_1
+    %val0_tmp = load i32, i32* @var32_0
+    %val1_tmp = load i32, i32* @var32_1
     %val2_tmp = add i32 1, %val1_tmp
     %val4_tmp = shl i32 %val0_tmp, %val2_tmp
 ; CHECK: {{lsl|lslv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
@@ -93,8 +93,8 @@ define void @lslv_i32() {
 
 define void @rorv_i32() {
 ; CHECK-LABEL: rorv_i32:
-    %val0_tmp = load i32* @var32_0
-    %val6_tmp = load i32* @var32_1
+    %val0_tmp = load i32, i32* @var32_0
+    %val6_tmp = load i32, i32* @var32_1
     %val1_tmp = add i32 1, %val6_tmp
     %val2_tmp = sub i32 32, %val1_tmp
     %val3_tmp = shl i32 %val0_tmp, %val2_tmp
@@ -107,8 +107,8 @@ define void @rorv_i32() {
 
 define void @asrv_i32() {
 ; CHECK-LABEL: asrv_i32:
-    %val0_tmp = load i32* @var32_0
-    %val1_tmp = load i32* @var32_1
+    %val0_tmp = load i32, i32* @var32_0
+    %val1_tmp = load i32, i32* @var32_1
     %val2_tmp = add i32 1, %val1_tmp
     %val4_tmp = ashr i32 %val0_tmp, %val2_tmp
 ; CHECK: {{asr|asrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
@@ -118,8 +118,8 @@ define void @asrv_i32() {
 
 define void @sdiv_i32() {
 ; CHECK-LABEL: sdiv_i32:
-    %val0_tmp = load i32* @var32_0
-    %val1_tmp = load i32* @var32_1
+    %val0_tmp = load i32, i32* @var32_0
+    %val1_tmp = load i32, i32* @var32_1
     %val4_tmp = sdiv i32 %val0_tmp, %val1_tmp
 ; CHECK: sdiv  {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
     store volatile i32 %val4_tmp, i32* @var32_1
@@ -128,8 +128,8 @@ define void @sdiv_i32() {
 
 define void @udiv_i32() {
 ; CHECK-LABEL: udiv_i32:
-    %val0_tmp = load i32* @var32_0
-    %val1_tmp = load i32* @var32_1
+    %val0_tmp = load i32, i32* @var32_0
+    %val1_tmp = load i32, i32* @var32_1
     %val4_tmp = udiv i32 %val0_tmp, %val1_tmp
 ; CHECK: udiv  {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
     store volatile i32 %val4_tmp, i32* @var32_0
@@ -141,7 +141,7 @@ define void @udiv_i32() {
 define i32 @test_lsl32() {
 ; CHECK-LABEL: test_lsl32:
 
-  %val = load i32* @var32_0
+  %val = load i32, i32* @var32_0
   %ret = shl i32 1, %val
 ; CHECK: {{lsl|lslv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
 
@@ -151,7 +151,7 @@ define i32 @test_lsl32() {
 define i32 @test_lsr32() {
 ; CHECK-LABEL: test_lsr32:
 
-  %val = load i32* @var32_0
+  %val = load i32, i32* @var32_0
   %ret = lshr i32 1, %val
 ; CHECK: {{lsr|lsrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
 
@@ -161,7 +161,7 @@ define i32 @test_lsr32() {
 define i32 @test_asr32(i32 %in) {
 ; CHECK-LABEL: test_asr32:
 
-  %val = load i32* @var32_0
+  %val = load i32, i32* @var32_0
   %ret = ashr i32 %in, %val
 ; CHECK: {{asr|asrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}