[AArch64] Don't assert when combining (v3f32 select (setcc f64)).

[oota-llvm.git] / test / CodeGen / AArch64 / half.ll

diff --git a/test/CodeGen/AArch64/half.ll b/test/CodeGen/AArch64/half.ll
index a46094b9fb85dfe97aee1aded1a32235da0f20f9..d4cbbc918a840912938ed2f67812fb763980cdf8 100644 (file)
--- a/test/CodeGen/AArch64/half.ll
+++ b/test/CodeGen/AArch64/half.ll
@@ -4,7 +4,7 @@ define void @test_load_store(half* %in, half* %out) {
 ; CHECK-LABEL: test_load_store:
 ; CHECK: ldr [[TMP:h[0-9]+]], [x0]
 ; CHECK: str [[TMP]], [x1]
-  %val = load half* %in
+  %val = load half, half* %in
   store half %val, half* %out
   ret void
 }
@@ -12,7 +12,7 @@ define void @test_load_store(half* %in, half* %out) {
 define i16 @test_bitcast_from_half(half* %addr) {
 ; CHECK-LABEL: test_bitcast_from_half:
 ; CHECK: ldrh w0, [x0]
-  %val = load half* %addr
+  %val = load half, half* %addr
   %val_int = bitcast half %val to i16
   ret i16 %val_int
 }
@@ -50,7 +50,7 @@ define float @test_extend32(half* %addr) {
 ; CHECK-LABEL: test_extend32:
 ; CHECK: fcvt {{s[0-9]+}}, {{h[0-9]+}}
 
-  %val16 = load half* %addr
+  %val16 = load half, half* %addr
   %val32 = fpext half %val16 to float
   ret float %val32
 }
@@ -59,7 +59,7 @@ define double @test_extend64(half* %addr) {
 ; CHECK-LABEL: test_extend64:
 ; CHECK: fcvt {{d[0-9]+}}, {{h[0-9]+}}
 
-  %val16 = load half* %addr
+  %val16 = load half, half* %addr
   %val32 = fpext half %val16 to double
   ret double %val32
 }