%res = bitcast i64 %in to <1 x double>
; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
ret <1 x double> %res
+}
+
+define <1 x i64> @test_bitcastv8i8tov1f64(<8 x i8> %a) #0 {
+; CHECK-LABEL: test_bitcastv8i8tov1f64:
+; CHECK: neg {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK-NEXT: fcvtzs {{d[0-9]+}}, {{d[0-9]+}}
+ %sub.i = sub <8 x i8> zeroinitializer, %a
+ %1 = bitcast <8 x i8> %sub.i to <1 x double>
+ %vcvt.i = fptosi <1 x double> %1 to <1 x i64>
+ ret <1 x i64> %vcvt.i
+}
+
+define <1 x i64> @test_bitcastv4i16tov1f64(<4 x i16> %a) #0 {
+; CHECK-LABEL: test_bitcastv4i16tov1f64:
+; CHECK: neg {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK-NEXT: fcvtzs {{d[0-9]+}}, {{d[0-9]+}}
+ %sub.i = sub <4 x i16> zeroinitializer, %a
+ %1 = bitcast <4 x i16> %sub.i to <1 x double>
+ %vcvt.i = fptosi <1 x double> %1 to <1 x i64>
+ ret <1 x i64> %vcvt.i
+}
+
+define <1 x i64> @test_bitcastv2i32tov1f64(<2 x i32> %a) #0 {
+; CHECK-LABEL: test_bitcastv2i32tov1f64:
+; CHECK: neg {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK-NEXT: fcvtzs {{d[0-9]+}}, {{d[0-9]+}}
+ %sub.i = sub <2 x i32> zeroinitializer, %a
+ %1 = bitcast <2 x i32> %sub.i to <1 x double>
+ %vcvt.i = fptosi <1 x double> %1 to <1 x i64>
+ ret <1 x i64> %vcvt.i
+}
+
+define <1 x i64> @test_bitcastv1i64tov1f64(<1 x i64> %a) #0 {
+; CHECK-LABEL: test_bitcastv1i64tov1f64:
+; CHECK: neg {{d[0-9]+}}, {{d[0-9]+}}
+; CHECK-NEXT: fcvtzs {{d[0-9]+}}, {{d[0-9]+}}
+ %sub.i = sub <1 x i64> zeroinitializer, %a
+ %1 = bitcast <1 x i64> %sub.i to <1 x double>
+ %vcvt.i = fptosi <1 x double> %1 to <1 x i64>
+ ret <1 x i64> %vcvt.i
+}
+
+define <1 x i64> @test_bitcastv2f32tov1f64(<2 x float> %a) #0 {
+; CHECK-LABEL: test_bitcastv2f32tov1f64:
+; CHECK: fneg {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK-NEXT: fcvtzs {{d[0-9]+}}, {{d[0-9]+}}
+ %sub.i = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %a
+ %1 = bitcast <2 x float> %sub.i to <1 x double>
+ %vcvt.i = fptosi <1 x double> %1 to <1 x i64>
+ ret <1 x i64> %vcvt.i
+}
+
+define <8 x i8> @test_bitcastv1f64tov8i8(<1 x i64> %a) #0 {
+; CHECK-LABEL: test_bitcastv1f64tov8i8:
+; CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}
+; CHECK-NEXT: neg {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+ %vcvt.i = sitofp <1 x i64> %a to <1 x double>
+ %1 = bitcast <1 x double> %vcvt.i to <8 x i8>
+ %sub.i = sub <8 x i8> zeroinitializer, %1
+ ret <8 x i8> %sub.i
+}
+
+define <4 x i16> @test_bitcastv1f64tov4i16(<1 x i64> %a) #0 {
+; CHECK-LABEL: test_bitcastv1f64tov4i16:
+; CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}
+; CHECK-NEXT: neg {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+ %vcvt.i = sitofp <1 x i64> %a to <1 x double>
+ %1 = bitcast <1 x double> %vcvt.i to <4 x i16>
+ %sub.i = sub <4 x i16> zeroinitializer, %1
+ ret <4 x i16> %sub.i
+}
+
+define <2 x i32> @test_bitcastv1f64tov2i32(<1 x i64> %a) #0 {
+; CHECK-LABEL: test_bitcastv1f64tov2i32:
+; CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}
+; CHECK-NEXT: neg {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+ %vcvt.i = sitofp <1 x i64> %a to <1 x double>
+ %1 = bitcast <1 x double> %vcvt.i to <2 x i32>
+ %sub.i = sub <2 x i32> zeroinitializer, %1
+ ret <2 x i32> %sub.i
+}
+
+define <1 x i64> @test_bitcastv1f64tov1i64(<1 x i64> %a) #0 {
+; CHECK-LABEL: test_bitcastv1f64tov1i64:
+; CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}
+; CHECK-NEXT: neg {{d[0-9]+}}, {{d[0-9]+}}
+ %vcvt.i = sitofp <1 x i64> %a to <1 x double>
+ %1 = bitcast <1 x double> %vcvt.i to <1 x i64>
+ %sub.i = sub <1 x i64> zeroinitializer, %1
+ ret <1 x i64> %sub.i
+}
+
+define <2 x float> @test_bitcastv1f64tov2f32(<1 x i64> %a) #0 {
+; CHECK-LABEL: test_bitcastv1f64tov2f32:
+; CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}
+; CHECK-NEXT: fneg {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+ %vcvt.i = sitofp <1 x i64> %a to <1 x double>
+ %1 = bitcast <1 x double> %vcvt.i to <2 x float>
+ %sub.i = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %1
+ ret <2 x float> %sub.i
+}
+
+; Test insert element into an undef vector
+define <8 x i8> @scalar_to_vector.v8i8(i8 %a) {
+; CHECK-LABEL: scalar_to_vector.v8i8:
+; CHECK: ins {{v[0-9]+}}.b[0], {{w[0-9]+}}
+ %b = insertelement <8 x i8> undef, i8 %a, i32 0
+ ret <8 x i8> %b
+}
+
+define <16 x i8> @scalar_to_vector.v16i8(i8 %a) {
+; CHECK-LABEL: scalar_to_vector.v16i8:
+; CHECK: ins {{v[0-9]+}}.b[0], {{w[0-9]+}}
+ %b = insertelement <16 x i8> undef, i8 %a, i32 0
+ ret <16 x i8> %b
+}
+
+define <4 x i16> @scalar_to_vector.v4i16(i16 %a) {
+; CHECK-LABEL: scalar_to_vector.v4i16:
+; CHECK: ins {{v[0-9]+}}.h[0], {{w[0-9]+}}
+ %b = insertelement <4 x i16> undef, i16 %a, i32 0
+ ret <4 x i16> %b
+}
+
+define <8 x i16> @scalar_to_vector.v8i16(i16 %a) {
+; CHECK-LABEL: scalar_to_vector.v8i16:
+; CHECK: ins {{v[0-9]+}}.h[0], {{w[0-9]+}}
+ %b = insertelement <8 x i16> undef, i16 %a, i32 0
+ ret <8 x i16> %b
+}
+
+define <2 x i32> @scalar_to_vector.v2i32(i32 %a) {
+; CHECK-LABEL: scalar_to_vector.v2i32:
+; CHECK: ins {{v[0-9]+}}.s[0], {{w[0-9]+}}
+ %b = insertelement <2 x i32> undef, i32 %a, i32 0
+ ret <2 x i32> %b
+}
+
+define <4 x i32> @scalar_to_vector.v4i32(i32 %a) {
+; CHECK-LABEL: scalar_to_vector.v4i32:
+; CHECK: ins {{v[0-9]+}}.s[0], {{w[0-9]+}}
+ %b = insertelement <4 x i32> undef, i32 %a, i32 0
+ ret <4 x i32> %b
+}
+
+define <2 x i64> @scalar_to_vector.v2i64(i64 %a) {
+; CHECK-LABEL: scalar_to_vector.v2i64:
+; CHECK: ins {{v[0-9]+}}.d[0], {{x[0-9]+}}
+ %b = insertelement <2 x i64> undef, i64 %a, i32 0
+ ret <2 x i64> %b
+}
+
+define <8 x i8> @testDUP.v1i8(<1 x i8> %a) {
+; CHECK-LABEL: testDUP.v1i8:
+; CHECK: dup {{v[0-9]+}}.8b, {{w[0-9]+}}
+ %b = extractelement <1 x i8> %a, i32 0
+ %c = insertelement <8 x i8> undef, i8 %b, i32 0
+ %d = insertelement <8 x i8> %c, i8 %b, i32 1
+ %e = insertelement <8 x i8> %d, i8 %b, i32 2
+ %f = insertelement <8 x i8> %e, i8 %b, i32 3
+ %g = insertelement <8 x i8> %f, i8 %b, i32 4
+ %h = insertelement <8 x i8> %g, i8 %b, i32 5
+ %i = insertelement <8 x i8> %h, i8 %b, i32 6
+ %j = insertelement <8 x i8> %i, i8 %b, i32 7
+ ret <8 x i8> %j
+}
+
+define <8 x i16> @testDUP.v1i16(<1 x i16> %a) {
+; CHECK-LABEL: testDUP.v1i16:
+; CHECK: dup {{v[0-9]+}}.8h, {{w[0-9]+}}
+ %b = extractelement <1 x i16> %a, i32 0
+ %c = insertelement <8 x i16> undef, i16 %b, i32 0
+ %d = insertelement <8 x i16> %c, i16 %b, i32 1
+ %e = insertelement <8 x i16> %d, i16 %b, i32 2
+ %f = insertelement <8 x i16> %e, i16 %b, i32 3
+ %g = insertelement <8 x i16> %f, i16 %b, i32 4
+ %h = insertelement <8 x i16> %g, i16 %b, i32 5
+ %i = insertelement <8 x i16> %h, i16 %b, i32 6
+ %j = insertelement <8 x i16> %i, i16 %b, i32 7
+ ret <8 x i16> %j
+}
+
+define <4 x i32> @testDUP.v1i32(<1 x i32> %a) {
+; CHECK-LABEL: testDUP.v1i32:
+; CHECK: dup {{v[0-9]+}}.4s, {{w[0-9]+}}
+ %b = extractelement <1 x i32> %a, i32 0
+ %c = insertelement <4 x i32> undef, i32 %b, i32 0
+ %d = insertelement <4 x i32> %c, i32 %b, i32 1
+ %e = insertelement <4 x i32> %d, i32 %b, i32 2
+ %f = insertelement <4 x i32> %e, i32 %b, i32 3
+ ret <4 x i32> %f
+}
+
+define <8 x i8> @getl(<16 x i8> %x) #0 {
+; CHECK-LABEL: getl:
+; CHECK: ret
+ %vecext = extractelement <16 x i8> %x, i32 0
+ %vecinit = insertelement <8 x i8> undef, i8 %vecext, i32 0
+ %vecext1 = extractelement <16 x i8> %x, i32 1
+ %vecinit2 = insertelement <8 x i8> %vecinit, i8 %vecext1, i32 1
+ %vecext3 = extractelement <16 x i8> %x, i32 2
+ %vecinit4 = insertelement <8 x i8> %vecinit2, i8 %vecext3, i32 2
+ %vecext5 = extractelement <16 x i8> %x, i32 3
+ %vecinit6 = insertelement <8 x i8> %vecinit4, i8 %vecext5, i32 3
+ %vecext7 = extractelement <16 x i8> %x, i32 4
+ %vecinit8 = insertelement <8 x i8> %vecinit6, i8 %vecext7, i32 4
+ %vecext9 = extractelement <16 x i8> %x, i32 5
+ %vecinit10 = insertelement <8 x i8> %vecinit8, i8 %vecext9, i32 5
+ %vecext11 = extractelement <16 x i8> %x, i32 6
+ %vecinit12 = insertelement <8 x i8> %vecinit10, i8 %vecext11, i32 6
+ %vecext13 = extractelement <16 x i8> %x, i32 7
+ %vecinit14 = insertelement <8 x i8> %vecinit12, i8 %vecext13, i32 7
+ ret <8 x i8> %vecinit14
+}
+
+define <4 x i16> @test_dup_v2i32_v4i16(<2 x i32> %a) {
+; CHECK-LABEL: test_dup_v2i32_v4i16:
+; CHECK: dup v0.4h, v0.h[2]
+entry:
+ %x = extractelement <2 x i32> %a, i32 1
+ %vget_lane = trunc i32 %x to i16
+ %vecinit.i = insertelement <4 x i16> undef, i16 %vget_lane, i32 0
+ %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %vget_lane, i32 1
+ %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %vget_lane, i32 2
+ %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %vget_lane, i32 3
+ ret <4 x i16> %vecinit3.i
+}
+
+define <8 x i16> @test_dup_v4i32_v8i16(<4 x i32> %a) {
+; CHECK-LABEL: test_dup_v4i32_v8i16:
+; CHECK: dup v0.8h, v0.h[6]
+entry:
+ %x = extractelement <4 x i32> %a, i32 3
+ %vget_lane = trunc i32 %x to i16
+ %vecinit.i = insertelement <8 x i16> undef, i16 %vget_lane, i32 0
+ %vecinit1.i = insertelement <8 x i16> %vecinit.i, i16 %vget_lane, i32 1
+ %vecinit2.i = insertelement <8 x i16> %vecinit1.i, i16 %vget_lane, i32 2
+ %vecinit3.i = insertelement <8 x i16> %vecinit2.i, i16 %vget_lane, i32 3
+ %vecinit4.i = insertelement <8 x i16> %vecinit3.i, i16 %vget_lane, i32 4
+ %vecinit5.i = insertelement <8 x i16> %vecinit4.i, i16 %vget_lane, i32 5
+ %vecinit6.i = insertelement <8 x i16> %vecinit5.i, i16 %vget_lane, i32 6
+ %vecinit7.i = insertelement <8 x i16> %vecinit6.i, i16 %vget_lane, i32 7
+ ret <8 x i16> %vecinit7.i
+}
+
+define <4 x i16> @test_dup_v1i64_v4i16(<1 x i64> %a) {
+; CHECK-LABEL: test_dup_v1i64_v4i16:
+; CHECK: dup v0.4h, v0.h[0]
+entry:
+ %x = extractelement <1 x i64> %a, i32 0
+ %vget_lane = trunc i64 %x to i16
+ %vecinit.i = insertelement <4 x i16> undef, i16 %vget_lane, i32 0
+ %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %vget_lane, i32 1
+ %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %vget_lane, i32 2
+ %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %vget_lane, i32 3
+ ret <4 x i16> %vecinit3.i
+}
+
+define <2 x i32> @test_dup_v1i64_v2i32(<1 x i64> %a) {
+; CHECK-LABEL: test_dup_v1i64_v2i32:
+; CHECK: dup v0.2s, v0.s[0]
+entry:
+ %x = extractelement <1 x i64> %a, i32 0
+ %vget_lane = trunc i64 %x to i32
+ %vecinit.i = insertelement <2 x i32> undef, i32 %vget_lane, i32 0
+ %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %vget_lane, i32 1
+ ret <2 x i32> %vecinit1.i
+}
+
+define <8 x i16> @test_dup_v2i64_v8i16(<2 x i64> %a) {
+; CHECK-LABEL: test_dup_v2i64_v8i16:
+; CHECK: dup v0.8h, v0.h[4]
+entry:
+ %x = extractelement <2 x i64> %a, i32 1
+ %vget_lane = trunc i64 %x to i16
+ %vecinit.i = insertelement <8 x i16> undef, i16 %vget_lane, i32 0
+ %vecinit1.i = insertelement <8 x i16> %vecinit.i, i16 %vget_lane, i32 1
+ %vecinit2.i = insertelement <8 x i16> %vecinit1.i, i16 %vget_lane, i32 2
+ %vecinit3.i = insertelement <8 x i16> %vecinit2.i, i16 %vget_lane, i32 3
+ %vecinit4.i = insertelement <8 x i16> %vecinit3.i, i16 %vget_lane, i32 4
+ %vecinit5.i = insertelement <8 x i16> %vecinit4.i, i16 %vget_lane, i32 5
+ %vecinit6.i = insertelement <8 x i16> %vecinit5.i, i16 %vget_lane, i32 6
+ %vecinit7.i = insertelement <8 x i16> %vecinit6.i, i16 %vget_lane, i32 7
+ ret <8 x i16> %vecinit7.i
+}
+
+define <4 x i32> @test_dup_v2i64_v4i32(<2 x i64> %a) {
+; CHECK-LABEL: test_dup_v2i64_v4i32:
+; CHECK: dup v0.4s, v0.s[2]
+entry:
+ %x = extractelement <2 x i64> %a, i32 1
+ %vget_lane = trunc i64 %x to i32
+ %vecinit.i = insertelement <4 x i32> undef, i32 %vget_lane, i32 0
+ %vecinit1.i = insertelement <4 x i32> %vecinit.i, i32 %vget_lane, i32 1
+ %vecinit2.i = insertelement <4 x i32> %vecinit1.i, i32 %vget_lane, i32 2
+ %vecinit3.i = insertelement <4 x i32> %vecinit2.i, i32 %vget_lane, i32 3
+ ret <4 x i32> %vecinit3.i
+}
+
+define <4 x i16> @test_dup_v4i32_v4i16(<4 x i32> %a) {
+; CHECK-LABEL: test_dup_v4i32_v4i16:
+; CHECK: dup v0.4h, v0.h[2]
+entry:
+ %x = extractelement <4 x i32> %a, i32 1
+ %vget_lane = trunc i32 %x to i16
+ %vecinit.i = insertelement <4 x i16> undef, i16 %vget_lane, i32 0
+ %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %vget_lane, i32 1
+ %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %vget_lane, i32 2
+ %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %vget_lane, i32 3
+ ret <4 x i16> %vecinit3.i
+}
+
+define <4 x i16> @test_dup_v2i64_v4i16(<2 x i64> %a) {
+; CHECK-LABEL: test_dup_v2i64_v4i16:
+; CHECK: dup v0.4h, v0.h[0]
+entry:
+ %x = extractelement <2 x i64> %a, i32 0
+ %vget_lane = trunc i64 %x to i16
+ %vecinit.i = insertelement <4 x i16> undef, i16 %vget_lane, i32 0
+ %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %vget_lane, i32 1
+ %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %vget_lane, i32 2
+ %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %vget_lane, i32 3
+ ret <4 x i16> %vecinit3.i
+}
+
+define <2 x i32> @test_dup_v2i64_v2i32(<2 x i64> %a) {
+; CHECK-LABEL: test_dup_v2i64_v2i32:
+; CHECK: dup v0.2s, v0.s[0]
+entry:
+ %x = extractelement <2 x i64> %a, i32 0
+ %vget_lane = trunc i64 %x to i32
+ %vecinit.i = insertelement <2 x i32> undef, i32 %vget_lane, i32 0
+ %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %vget_lane, i32 1
+ ret <2 x i32> %vecinit1.i
+}
+
+define <2 x i32> @test_concat_undef_v1i32(<1 x i32> %a) {
+; CHECK-LABEL: test_concat_undef_v1i32:
+; CHECK: dup v{{[0-9]+}}.2s, v{{[0-9]+}}.s[0]
+entry:
+ %0 = extractelement <1 x i32> %a, i32 0
+ %vecinit1.i = insertelement <2 x i32> undef, i32 %0, i32 1
+ ret <2 x i32> %vecinit1.i
+}
+
+define <2 x i32> @test_concat_v1i32_v1i32(<1 x i32> %a) {
+; CHECK-LABEL: test_concat_v1i32_v1i32:
+; CHECK: dup v{{[0-9]+}}.2s, v{{[0-9]+}}.s[0]
+entry:
+ %0 = extractelement <1 x i32> %a, i32 0
+ %vecinit.i = insertelement <2 x i32> undef, i32 %0, i32 0
+ %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %0, i32 1
+ ret <2 x i32> %vecinit1.i
+}
+
+define <2 x float> @test_scalar_to_vector_f32_to_v2f32(<1 x float> %a) {
+entry:
+ %0 = extractelement <1 x float> %a, i32 0
+ %vecinit1.i = insertelement <2 x float> undef, float %0, i32 0
+ ret <2 x float> %vecinit1.i
+}
+
+define <4 x float> @test_scalar_to_vector_f32_to_v4f32(<1 x float> %a) {
+entry:
+ %0 = extractelement <1 x float> %a, i32 0
+ %vecinit1.i = insertelement <4 x float> undef, float %0, i32 0
+ ret <4 x float> %vecinit1.i
}
\ No newline at end of file
projects / oota-llvm.git / blobdiff