ARM: use the proper target object format for WoA

[oota-llvm.git] / test / CodeGen / AArch64 / neon-simd-ldst-one.ll

diff --git a/test/CodeGen/AArch64/neon-simd-ldst-one.ll b/test/CodeGen/AArch64/neon-simd-ldst-one.ll
index 0ec5876325da99235da2484954574bf34a409254..75c2a82ab57e93d24b97d5d782c153171794fcaa 100644 (file)
--- a/test/CodeGen/AArch64/neon-simd-ldst-one.ll
+++ b/test/CodeGen/AArch64/neon-simd-ldst-one.ll
@@ -124,7 +124,7 @@ entry:
 
 define <16 x i8> @test_vld1q_dup_s8(i8* %a) {
 ; CHECK-LABEL: test_vld1q_dup_s8
-; CHECK: ld1r {{{v[0-9]+}}.16b}, [x0]
+; CHECK: ld1r { {{v[0-9]+}}.16b }, [x0]
 entry:
   %0 = load i8* %a, align 1
   %1 = insertelement <16 x i8> undef, i8 %0, i32 0
@@ -134,7 +134,7 @@ entry:
 
 define <8 x i16> @test_vld1q_dup_s16(i16* %a) {
 ; CHECK-LABEL: test_vld1q_dup_s16
-; CHECK: ld1r {{{v[0-9]+}}.8h}, [x0]
+; CHECK: ld1r { {{v[0-9]+}}.8h }, [x0]
 entry:
   %0 = load i16* %a, align 2
   %1 = insertelement <8 x i16> undef, i16 %0, i32 0
@@ -144,7 +144,7 @@ entry:
 
 define <4 x i32> @test_vld1q_dup_s32(i32* %a) {
 ; CHECK-LABEL: test_vld1q_dup_s32
-; CHECK: ld1r {{{v[0-9]+}}.4s}, [x0]
+; CHECK: ld1r { {{v[0-9]+}}.4s }, [x0]
 entry:
   %0 = load i32* %a, align 4
   %1 = insertelement <4 x i32> undef, i32 %0, i32 0
@@ -154,7 +154,7 @@ entry:
 
 define <2 x i64> @test_vld1q_dup_s64(i64* %a) {
 ; CHECK-LABEL: test_vld1q_dup_s64
-; CHECK: ld1r {{{v[0-9]+}}.2d}, [x0]
+; CHECK: ld1r { {{v[0-9]+}}.2d }, [x0]
 entry:
   %0 = load i64* %a, align 8
   %1 = insertelement <2 x i64> undef, i64 %0, i32 0
@@ -164,7 +164,7 @@ entry:
 
 define <4 x float> @test_vld1q_dup_f32(float* %a) {
 ; CHECK-LABEL: test_vld1q_dup_f32
-; CHECK: ld1r {{{v[0-9]+}}.4s}, [x0]
+; CHECK: ld1r { {{v[0-9]+}}.4s }, [x0]
 entry:
   %0 = load float* %a, align 4
   %1 = insertelement <4 x float> undef, float %0, i32 0
@@ -174,7 +174,7 @@ entry:
 
 define <2 x double> @test_vld1q_dup_f64(double* %a) {
 ; CHECK-LABEL: test_vld1q_dup_f64
-; CHECK: ld1r {{{v[0-9]+}}.2d}, [x0]
+; CHECK: ld1r { {{v[0-9]+}}.2d }, [x0]
 entry:
   %0 = load double* %a, align 8
   %1 = insertelement <2 x double> undef, double %0, i32 0
@@ -184,7 +184,7 @@ entry:
 
 define <8 x i8> @test_vld1_dup_s8(i8* %a) {
 ; CHECK-LABEL: test_vld1_dup_s8
-; CHECK: ld1r {{{v[0-9]+}}.8b}, [x0]
+; CHECK: ld1r { {{v[0-9]+}}.8b }, [x0]
 entry:
   %0 = load i8* %a, align 1
   %1 = insertelement <8 x i8> undef, i8 %0, i32 0
@@ -194,7 +194,7 @@ entry:
 
 define <4 x i16> @test_vld1_dup_s16(i16* %a) {
 ; CHECK-LABEL: test_vld1_dup_s16
-; CHECK: ld1r {{{v[0-9]+}}.4h}, [x0]
+; CHECK: ld1r { {{v[0-9]+}}.4h }, [x0]
 entry:
   %0 = load i16* %a, align 2
   %1 = insertelement <4 x i16> undef, i16 %0, i32 0
@@ -204,7 +204,7 @@ entry:
 
 define <2 x i32> @test_vld1_dup_s32(i32* %a) {
 ; CHECK-LABEL: test_vld1_dup_s32
-; CHECK: ld1r {{{v[0-9]+}}.2s}, [x0]
+; CHECK: ld1r { {{v[0-9]+}}.2s }, [x0]
 entry:
   %0 = load i32* %a, align 4
   %1 = insertelement <2 x i32> undef, i32 %0, i32 0
@@ -214,7 +214,7 @@ entry:
 
 define <1 x i64> @test_vld1_dup_s64(i64* %a) {
 ; CHECK-LABEL: test_vld1_dup_s64
-; CHECK: ld1r {{{v[0-9]+}}.1d}, [x0]
+; CHECK: ld1r { {{v[0-9]+}}.1d }, [x0]
 entry:
   %0 = load i64* %a, align 8
   %1 = insertelement <1 x i64> undef, i64 %0, i32 0
@@ -223,7 +223,7 @@ entry:
 
 define <2 x float> @test_vld1_dup_f32(float* %a) {
 ; CHECK-LABEL: test_vld1_dup_f32
-; CHECK: ld1r {{{v[0-9]+}}.2s}, [x0]
+; CHECK: ld1r { {{v[0-9]+}}.2s }, [x0]
 entry:
   %0 = load float* %a, align 4
   %1 = insertelement <2 x float> undef, float %0, i32 0
@@ -233,7 +233,7 @@ entry:
 
 define <1 x double> @test_vld1_dup_f64(double* %a) {
 ; CHECK-LABEL: test_vld1_dup_f64
-; CHECK: ld1r {{{v[0-9]+}}.1d}, [x0]
+; CHECK: ld1r { {{v[0-9]+}}.1d }, [x0]
 entry:
   %0 = load double* %a, align 8
   %1 = insertelement <1 x double> undef, double %0, i32 0
@@ -267,7 +267,7 @@ define <1 x double> @testDUP.v1f64(double* %a, double* %b) #0 {
 
 define %struct.int8x16x2_t @test_vld2q_dup_s8(i8* %a) {
 ; CHECK-LABEL: test_vld2q_dup_s8
-; CHECK: ld2r {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, [x0]
+; CHECK: ld2r { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, [x0]
 entry:
   %vld_dup = tail call { <16 x i8>, <16 x i8> } @llvm.arm.neon.vld2lane.v16i8(i8* %a, <16 x i8> undef, <16 x i8> undef, i32 0, i32 1)
   %0 = extractvalue { <16 x i8>, <16 x i8> } %vld_dup, 0
@@ -281,7 +281,7 @@ entry:
 
 define %struct.int16x8x2_t @test_vld2q_dup_s16(i16* %a) {
 ; CHECK-LABEL: test_vld2q_dup_s16
-; CHECK: ld2r {{{v[0-9]+}}.8h, {{v[0-9]+}}.8h}, [x0]
+; CHECK: ld2r { {{v[0-9]+}}.8h, {{v[0-9]+}}.8h }, [x0]
 entry:
   %0 = bitcast i16* %a to i8*
   %vld_dup = tail call { <8 x i16>, <8 x i16> } @llvm.arm.neon.vld2lane.v8i16(i8* %0, <8 x i16> undef, <8 x i16> undef, i32 0, i32 2)
@@ -296,7 +296,7 @@ entry:
 
 define %struct.int32x4x2_t @test_vld2q_dup_s32(i32* %a) {
 ; CHECK-LABEL: test_vld2q_dup_s32
-; CHECK: ld2r {{{v[0-9]+}}.4s, {{v[0-9]+}}.4s}, [x0]
+; CHECK: ld2r { {{v[0-9]+}}.4s, {{v[0-9]+}}.4s }, [x0]
 entry:
   %0 = bitcast i32* %a to i8*
   %vld_dup = tail call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2lane.v4i32(i8* %0, <4 x i32> undef, <4 x i32> undef, i32 0, i32 4)
@@ -311,7 +311,7 @@ entry:
 
 define %struct.int64x2x2_t @test_vld2q_dup_s64(i64* %a) {
 ; CHECK-LABEL: test_vld2q_dup_s64
-; CHECK: ld2r {{{v[0-9]+}}.2d, {{v[0-9]+}}.2d}, [x0]
+; CHECK: ld2r { {{v[0-9]+}}.2d, {{v[0-9]+}}.2d }, [x0]
 entry:
   %0 = bitcast i64* %a to i8*
   %vld_dup = tail call { <2 x i64>, <2 x i64> } @llvm.arm.neon.vld2lane.v2i64(i8* %0, <2 x i64> undef, <2 x i64> undef, i32 0, i32 8)
@@ -326,7 +326,7 @@ entry:
 
 define %struct.float32x4x2_t @test_vld2q_dup_f32(float* %a) {
 ; CHECK-LABEL: test_vld2q_dup_f32
-; CHECK: ld2r {{{v[0-9]+}}.4s, {{v[0-9]+}}.4s}, [x0]
+; CHECK: ld2r { {{v[0-9]+}}.4s, {{v[0-9]+}}.4s }, [x0]
 entry:
   %0 = bitcast float* %a to i8*
   %vld_dup = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2lane.v4f32(i8* %0, <4 x float> undef, <4 x float> undef, i32 0, i32 4)
@@ -341,7 +341,7 @@ entry:
 
 define %struct.float64x2x2_t @test_vld2q_dup_f64(double* %a) {
 ; CHECK-LABEL: test_vld2q_dup_f64
-; CHECK: ld2r {{{v[0-9]+}}.2d, {{v[0-9]+}}.2d}, [x0]
+; CHECK: ld2r { {{v[0-9]+}}.2d, {{v[0-9]+}}.2d }, [x0]
 entry:
   %0 = bitcast double* %a to i8*
   %vld_dup = tail call { <2 x double>, <2 x double> } @llvm.arm.neon.vld2lane.v2f64(i8* %0, <2 x double> undef, <2 x double> undef, i32 0, i32 8)
@@ -356,7 +356,7 @@ entry:
 
 define %struct.int8x8x2_t @test_vld2_dup_s8(i8* %a) {
 ; CHECK-LABEL: test_vld2_dup_s8
-; CHECK: ld2r {{{v[0-9]+}}.8b, {{v[0-9]+}}.8b}, [x0]
+; CHECK: ld2r { {{v[0-9]+}}.8b, {{v[0-9]+}}.8b }, [x0]
 entry:
   %vld_dup = tail call { <8 x i8>, <8 x i8> } @llvm.arm.neon.vld2lane.v8i8(i8* %a, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1)
   %0 = extractvalue { <8 x i8>, <8 x i8> } %vld_dup, 0
@@ -370,7 +370,7 @@ entry:
 
 define %struct.int16x4x2_t @test_vld2_dup_s16(i16* %a) {
 ; CHECK-LABEL: test_vld2_dup_s16
-; CHECK: ld2r {{{v[0-9]+}}.4h, {{v[0-9]+}}.4h}, [x0]
+; CHECK: ld2r { {{v[0-9]+}}.4h, {{v[0-9]+}}.4h }, [x0]
 entry:
   %0 = bitcast i16* %a to i8*
   %vld_dup = tail call { <4 x i16>, <4 x i16> } @llvm.arm.neon.vld2lane.v4i16(i8* %0, <4 x i16> undef, <4 x i16> undef, i32 0, i32 2)
@@ -385,7 +385,7 @@ entry:
 
 define %struct.int32x2x2_t @test_vld2_dup_s32(i32* %a) {
 ; CHECK-LABEL: test_vld2_dup_s32
-; CHECK: ld2r {{{v[0-9]+}}.2s, {{v[0-9]+}}.2s}, [x0]
+; CHECK: ld2r { {{v[0-9]+}}.2s, {{v[0-9]+}}.2s }, [x0]
 entry:
   %0 = bitcast i32* %a to i8*
   %vld_dup = tail call { <2 x i32>, <2 x i32> } @llvm.arm.neon.vld2lane.v2i32(i8* %0, <2 x i32> undef, <2 x i32> undef, i32 0, i32 4)
@@ -400,7 +400,7 @@ entry:
 
 define %struct.int64x1x2_t @test_vld2_dup_s64(i64* %a) {
 ; CHECK-LABEL: test_vld2_dup_s64
-; CHECK: ld1 {{{v[0-9]+}}.1d, {{v[0-9]+}}.1d}, [x0]
+; CHECK: ld1 { {{v[0-9]+}}.1d, {{v[0-9]+}}.1d }, [x0]
 entry:
   %0 = bitcast i64* %a to i8*
   %vld_dup = tail call { <1 x i64>, <1 x i64> } @llvm.arm.neon.vld2.v1i64(i8* %0, i32 8)
@@ -413,7 +413,7 @@ entry:
 
 define %struct.float32x2x2_t @test_vld2_dup_f32(float* %a) {
 ; CHECK-LABEL: test_vld2_dup_f32
-; CHECK: ld2r {{{v[0-9]+}}.2s, {{v[0-9]+}}.2s}, [x0]
+; CHECK: ld2r { {{v[0-9]+}}.2s, {{v[0-9]+}}.2s }, [x0]
 entry:
   %0 = bitcast float* %a to i8*
   %vld_dup = tail call { <2 x float>, <2 x float> } @llvm.arm.neon.vld2lane.v2f32(i8* %0, <2 x float> undef, <2 x float> undef, i32 0, i32 4)
@@ -428,7 +428,7 @@ entry:
 
 define %struct.float64x1x2_t @test_vld2_dup_f64(double* %a) {
 ; CHECK-LABEL: test_vld2_dup_f64
-; CHECK: ld1 {{{v[0-9]+}}.1d, {{v[0-9]+}}.1d}, [x0]
+; CHECK: ld1 { {{v[0-9]+}}.1d, {{v[0-9]+}}.1d }, [x0]
 entry:
   %0 = bitcast double* %a to i8*
   %vld_dup = tail call { <1 x double>, <1 x double> } @llvm.arm.neon.vld2.v1f64(i8* %0, i32 8)
@@ -441,7 +441,7 @@ entry:
 
 define %struct.int8x16x3_t @test_vld3q_dup_s8(i8* %a) {
 ; CHECK-LABEL: test_vld3q_dup_s8
-; CHECK: ld3r {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, [x0]
+; CHECK: ld3r { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, [x0]
 entry:
   %vld_dup = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3lane.v16i8(i8* %a, <16 x i8> undef, <16 x i8> undef, <16 x i8> undef, i32 0, i32 1)
   %0 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %vld_dup, 0
@@ -458,7 +458,7 @@ entry:
 
 define %struct.int16x8x3_t @test_vld3q_dup_s16(i16* %a) {
 ; CHECK-LABEL: test_vld3q_dup_s16
-; CHECK: ld3r {{{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h}, [x0]
+; CHECK: ld3r { {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h }, [x0]
 entry:
   %0 = bitcast i16* %a to i8*
   %vld_dup = tail call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16(i8* %0, <8 x i16> undef, <8 x i16> undef, <8 x i16> undef, i32 0, i32 2)
@@ -476,7 +476,7 @@ entry:
 
 define %struct.int32x4x3_t @test_vld3q_dup_s32(i32* %a) {
 ; CHECK-LABEL: test_vld3q_dup_s32
-; CHECK: ld3r {{{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s}, [x0]
+; CHECK: ld3r { {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s }, [x0]
 entry:
   %0 = bitcast i32* %a to i8*
   %vld_dup = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld3lane.v4i32(i8* %0, <4 x i32> undef, <4 x i32> undef, <4 x i32> undef, i32 0, i32 4)
@@ -494,7 +494,7 @@ entry:
 
 define %struct.int64x2x3_t @test_vld3q_dup_s64(i64* %a) {
 ; CHECK-LABEL: test_vld3q_dup_s64
-; CHECK: ld3r {{{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d}, [x0]
+; CHECK: ld3r { {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d }, [x0]
 entry:
   %0 = bitcast i64* %a to i8*
   %vld_dup = tail call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm.neon.vld3lane.v2i64(i8* %0, <2 x i64> undef, <2 x i64> undef, <2 x i64> undef, i32 0, i32 8)
@@ -512,7 +512,7 @@ entry:
 
 define %struct.float32x4x3_t @test_vld3q_dup_f32(float* %a) {
 ; CHECK-LABEL: test_vld3q_dup_f32
-; CHECK: ld3r {{{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s}, [x0]
+; CHECK: ld3r { {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s }, [x0]
 entry:
   %0 = bitcast float* %a to i8*
   %vld_dup = tail call { <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld3lane.v4f32(i8* %0, <4 x float> undef, <4 x float> undef, <4 x float> undef, i32 0, i32 4)
@@ -530,7 +530,7 @@ entry:
 
 define %struct.float64x2x3_t @test_vld3q_dup_f64(double* %a) {
 ; CHECK-LABEL: test_vld3q_dup_f64
-; CHECK: ld3r {{{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d}, [x0]
+; CHECK: ld3r { {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d }, [x0]
 entry:
   %0 = bitcast double* %a to i8*
   %vld_dup = tail call { <2 x double>, <2 x double>, <2 x double> } @llvm.arm.neon.vld3lane.v2f64(i8* %0, <2 x double> undef, <2 x double> undef, <2 x double> undef, i32 0, i32 8)
@@ -548,7 +548,7 @@ entry:
 
 define %struct.int8x8x3_t @test_vld3_dup_s8(i8* %a) {
 ; CHECK-LABEL: test_vld3_dup_s8
-; CHECK: ld3r {{{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b}, [x0]
+; CHECK: ld3r { {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b }, [x0]
 entry:
   %vld_dup = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld3lane.v8i8(i8* %a, <8 x i8> undef, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1)
   %0 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %vld_dup, 0
@@ -565,7 +565,7 @@ entry:
 
 define %struct.int16x4x3_t @test_vld3_dup_s16(i16* %a) {
 ; CHECK-LABEL: test_vld3_dup_s16
-; CHECK: ld3r {{{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h}, [x0]
+; CHECK: ld3r { {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h }, [x0]
 entry:
   %0 = bitcast i16* %a to i8*
   %vld_dup = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld3lane.v4i16(i8* %0, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 2)
@@ -583,7 +583,7 @@ entry:
 
 define %struct.int32x2x3_t @test_vld3_dup_s32(i32* %a) {
 ; CHECK-LABEL: test_vld3_dup_s32
-; CHECK: ld3r {{{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s}, [x0]
+; CHECK: ld3r { {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s }, [x0]
 entry:
   %0 = bitcast i32* %a to i8*
   %vld_dup = tail call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld3lane.v2i32(i8* %0, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, i32 0, i32 4)
@@ -601,7 +601,7 @@ entry:
 
 define %struct.int64x1x3_t @test_vld3_dup_s64(i64* %a) {
 ; CHECK-LABEL: test_vld3_dup_s64
-; CHECK: ld1 {{{v[0-9]+}}.1d, {{v[0-9]+}}.1d, {{v[0-9]+}}.1d}, [x0]
+; CHECK: ld1 { {{v[0-9]+}}.1d, {{v[0-9]+}}.1d, {{v[0-9]+}}.1d }, [x0]
 entry:
   %0 = bitcast i64* %a to i8*
   %vld_dup = tail call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm.neon.vld3.v1i64(i8* %0, i32 8)
@@ -616,7 +616,7 @@ entry:
 
 define %struct.float32x2x3_t @test_vld3_dup_f32(float* %a) {
 ; CHECK-LABEL: test_vld3_dup_f32
-; CHECK: ld3r {{{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s}, [x0]
+; CHECK: ld3r { {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s }, [x0]
 entry:
   %0 = bitcast float* %a to i8*
   %vld_dup = tail call { <2 x float>, <2 x float>, <2 x float> } @llvm.arm.neon.vld3lane.v2f32(i8* %0, <2 x float> undef, <2 x float> undef, <2 x float> undef, i32 0, i32 4)
@@ -634,7 +634,7 @@ entry:
 
 define %struct.float64x1x3_t @test_vld3_dup_f64(double* %a) {
 ; CHECK-LABEL: test_vld3_dup_f64
-; CHECK: ld1 {{{v[0-9]+}}.1d, {{v[0-9]+}}.1d, {{v[0-9]+}}.1d}, [x0]
+; CHECK: ld1 { {{v[0-9]+}}.1d, {{v[0-9]+}}.1d, {{v[0-9]+}}.1d }, [x0]
 entry:
   %0 = bitcast double* %a to i8*
   %vld_dup = tail call { <1 x double>, <1 x double>, <1 x double> } @llvm.arm.neon.vld3.v1f64(i8* %0, i32 8)
@@ -649,7 +649,7 @@ entry:
 
 define %struct.int8x16x4_t @test_vld4q_dup_s8(i8* %a) {
 ; CHECK-LABEL: test_vld4q_dup_s8
-; CHECK: ld4r {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, [x0]
+; CHECK: ld4r { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, [x0]
 entry:
   %vld_dup = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld4lane.v16i8(i8* %a, <16 x i8> undef, <16 x i8> undef, <16 x i8> undef, <16 x i8> undef, i32 0, i32 1)
   %0 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %vld_dup, 0
@@ -669,7 +669,7 @@ entry:
 
 define %struct.int16x8x4_t @test_vld4q_dup_s16(i16* %a) {
 ; CHECK-LABEL: test_vld4q_dup_s16
-; CHECK: ld4r {{{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h}, [x0]
+; CHECK: ld4r { {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h }, [x0]
 entry:
   %0 = bitcast i16* %a to i8*
   %vld_dup = tail call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld4lane.v8i16(i8* %0, <8 x i16> undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> undef, i32 0, i32 2)
@@ -690,7 +690,7 @@ entry:
 
 define %struct.int32x4x4_t @test_vld4q_dup_s32(i32* %a) {
 ; CHECK-LABEL: test_vld4q_dup_s32
-; CHECK: ld4r {{{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s}, [x0]
+; CHECK: ld4r { {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s }, [x0]
 entry:
   %0 = bitcast i32* %a to i8*
   %vld_dup = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld4lane.v4i32(i8* %0, <4 x i32> undef, <4 x i32> undef, <4 x i32> undef, <4 x i32> undef, i32 0, i32 4)
@@ -711,7 +711,7 @@ entry:
 
 define %struct.int64x2x4_t @test_vld4q_dup_s64(i64* %a) {
 ; CHECK-LABEL: test_vld4q_dup_s64
-; CHECK: ld4r {{{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d}, [x0]
+; CHECK: ld4r { {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d }, [x0]
 entry:
   %0 = bitcast i64* %a to i8*
   %vld_dup = tail call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm.neon.vld4lane.v2i64(i8* %0, <2 x i64> undef, <2 x i64> undef, <2 x i64> undef, <2 x i64> undef, i32 0, i32 8)
@@ -732,7 +732,7 @@ entry:
 
 define %struct.float32x4x4_t @test_vld4q_dup_f32(float* %a) {
 ; CHECK-LABEL: test_vld4q_dup_f32
-; CHECK: ld4r {{{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s}, [x0]
+; CHECK: ld4r { {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s }, [x0]
 entry:
   %0 = bitcast float* %a to i8*
   %vld_dup = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld4lane.v4f32(i8* %0, <4 x float> undef, <4 x float> undef, <4 x float> undef, <4 x float> undef, i32 0, i32 4)
@@ -753,7 +753,7 @@ entry:
 
 define %struct.float64x2x4_t @test_vld4q_dup_f64(double* %a) {
 ; CHECK-LABEL: test_vld4q_dup_f64
-; CHECK: ld4r {{{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d}, [x0]
+; CHECK: ld4r { {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d }, [x0]
 entry:
   %0 = bitcast double* %a to i8*
   %vld_dup = tail call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.arm.neon.vld4lane.v2f64(i8* %0, <2 x double> undef, <2 x double> undef, <2 x double> undef, <2 x double> undef, i32 0, i32 8)
@@ -774,7 +774,7 @@ entry:
 
 define %struct.int8x8x4_t @test_vld4_dup_s8(i8* %a) {
 ; CHECK-LABEL: test_vld4_dup_s8
-; CHECK: ld4r {{{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b}, [x0]
+; CHECK: ld4r { {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b }, [x0]
 entry:
   %vld_dup = tail call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld4lane.v8i8(i8* %a, <8 x i8> undef, <8 x i8> undef, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1)
   %0 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %vld_dup, 0
@@ -794,7 +794,7 @@ entry:
 
 define %struct.int16x4x4_t @test_vld4_dup_s16(i16* %a) {
 ; CHECK-LABEL: test_vld4_dup_s16
-; CHECK: ld4r {{{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h}, [x0]
+; CHECK: ld4r { {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h }, [x0]
 entry:
   %0 = bitcast i16* %a to i8*
   %vld_dup = tail call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld4lane.v4i16(i8* %0, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 2)
@@ -815,7 +815,7 @@ entry:
 
 define %struct.int32x2x4_t @test_vld4_dup_s32(i32* %a) {
 ; CHECK-LABEL: test_vld4_dup_s32
-; CHECK: ld4r {{{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s}, [x0]
+; CHECK: ld4r { {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s }, [x0]
 entry:
   %0 = bitcast i32* %a to i8*
   %vld_dup = tail call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld4lane.v2i32(i8* %0, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, i32 0, i32 4)
@@ -836,7 +836,7 @@ entry:
 
 define %struct.int64x1x4_t @test_vld4_dup_s64(i64* %a) {
 ; CHECK-LABEL: test_vld4_dup_s64
-; CHECK: ld1 {{{v[0-9]+}}.1d, {{v[0-9]+}}.1d, {{v[0-9]+}}.1d, {{v[0-9]+}}.1d}, [x0]
+; CHECK: ld1 { {{v[0-9]+}}.1d, {{v[0-9]+}}.1d, {{v[0-9]+}}.1d, {{v[0-9]+}}.1d }, [x0]
 entry:
   %0 = bitcast i64* %a to i8*
   %vld_dup = tail call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm.neon.vld4.v1i64(i8* %0, i32 8)
@@ -853,7 +853,7 @@ entry:
 
 define %struct.float32x2x4_t @test_vld4_dup_f32(float* %a) {
 ; CHECK-LABEL: test_vld4_dup_f32
-; CHECK: ld4r {{{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s}, [x0]
+; CHECK: ld4r { {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s }, [x0]
 entry:
   %0 = bitcast float* %a to i8*
   %vld_dup = tail call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.arm.neon.vld4lane.v2f32(i8* %0, <2 x float> undef, <2 x float> undef, <2 x float> undef, <2 x float> undef, i32 0, i32 4)
@@ -874,7 +874,7 @@ entry:
 
 define %struct.float64x1x4_t @test_vld4_dup_f64(double* %a) {
 ; CHECK-LABEL: test_vld4_dup_f64
-; CHECK: ld1 {{{v[0-9]+}}.1d, {{v[0-9]+}}.1d, {{v[0-9]+}}.1d, {{v[0-9]+}}.1d}, [x0]
+; CHECK: ld1 { {{v[0-9]+}}.1d, {{v[0-9]+}}.1d, {{v[0-9]+}}.1d, {{v[0-9]+}}.1d }, [x0]
 entry:
   %0 = bitcast double* %a to i8*
   %vld_dup = tail call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.arm.neon.vld4.v1f64(i8* %0, i32 8)
@@ -891,7 +891,7 @@ entry:
 
 define <16 x i8> @test_vld1q_lane_s8(i8* %a, <16 x i8> %b) {
 ; CHECK-LABEL: test_vld1q_lane_s8
-; CHECK: ld1 {{{v[0-9]+}}.b}[{{[0-9]+}}], [x0]
+; CHECK: ld1 { {{v[0-9]+}}.b }[{{[0-9]+}}], [x0]
 entry:
   %0 = load i8* %a, align 1
   %vld1_lane = insertelement <16 x i8> %b, i8 %0, i32 15
@@ -900,7 +900,7 @@ entry:
 
 define <8 x i16> @test_vld1q_lane_s16(i16* %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vld1q_lane_s16
-; CHECK: ld1 {{{v[0-9]+}}.h}[{{[0-9]+}}], [x0]
+; CHECK: ld1 { {{v[0-9]+}}.h }[{{[0-9]+}}], [x0]
 entry:
   %0 = load i16* %a, align 2
   %vld1_lane = insertelement <8 x i16> %b, i16 %0, i32 7
@@ -909,7 +909,7 @@ entry:
 
 define <4 x i32> @test_vld1q_lane_s32(i32* %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vld1q_lane_s32
-; CHECK: ld1 {{{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: ld1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %0 = load i32* %a, align 4
   %vld1_lane = insertelement <4 x i32> %b, i32 %0, i32 3
@@ -918,7 +918,7 @@ entry:
 
 define <2 x i64> @test_vld1q_lane_s64(i64* %a, <2 x i64> %b) {
 ; CHECK-LABEL: test_vld1q_lane_s64
-; CHECK: ld1 {{{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: ld1 { {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %0 = load i64* %a, align 8
   %vld1_lane = insertelement <2 x i64> %b, i64 %0, i32 1
@@ -927,7 +927,7 @@ entry:
 
 define <4 x float> @test_vld1q_lane_f32(float* %a, <4 x float> %b) {
 ; CHECK-LABEL: test_vld1q_lane_f32
-; CHECK: ld1 {{{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: ld1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %0 = load float* %a, align 4
   %vld1_lane = insertelement <4 x float> %b, float %0, i32 3
@@ -936,7 +936,7 @@ entry:
 
 define <2 x double> @test_vld1q_lane_f64(double* %a, <2 x double> %b) {
 ; CHECK-LABEL: test_vld1q_lane_f64
-; CHECK: ld1 {{{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: ld1 { {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %0 = load double* %a, align 8
   %vld1_lane = insertelement <2 x double> %b, double %0, i32 1
@@ -945,7 +945,7 @@ entry:
 
 define <8 x i8> @test_vld1_lane_s8(i8* %a, <8 x i8> %b) {
 ; CHECK-LABEL: test_vld1_lane_s8
-; CHECK: ld1 {{{v[0-9]+}}.b}[{{[0-9]+}}], [x0]
+; CHECK: ld1 { {{v[0-9]+}}.b }[{{[0-9]+}}], [x0]
 entry:
   %0 = load i8* %a, align 1
   %vld1_lane = insertelement <8 x i8> %b, i8 %0, i32 7
@@ -954,7 +954,7 @@ entry:
 
 define <4 x i16> @test_vld1_lane_s16(i16* %a, <4 x i16> %b) {
 ; CHECK-LABEL: test_vld1_lane_s16
-; CHECK: ld1 {{{v[0-9]+}}.h}[{{[0-9]+}}], [x0]
+; CHECK: ld1 { {{v[0-9]+}}.h }[{{[0-9]+}}], [x0]
 entry:
   %0 = load i16* %a, align 2
   %vld1_lane = insertelement <4 x i16> %b, i16 %0, i32 3
@@ -963,7 +963,7 @@ entry:
 
 define <2 x i32> @test_vld1_lane_s32(i32* %a, <2 x i32> %b) {
 ; CHECK-LABEL: test_vld1_lane_s32
-; CHECK: ld1 {{{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: ld1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %0 = load i32* %a, align 4
   %vld1_lane = insertelement <2 x i32> %b, i32 %0, i32 1
@@ -972,7 +972,7 @@ entry:
 
 define <1 x i64> @test_vld1_lane_s64(i64* %a, <1 x i64> %b) {
 ; CHECK-LABEL: test_vld1_lane_s64
-; CHECK: ld1r {{{v[0-9]+}}.1d}, [x0]
+; CHECK: ld1r { {{v[0-9]+}}.1d }, [x0]
 entry:
   %0 = load i64* %a, align 8
   %vld1_lane = insertelement <1 x i64> undef, i64 %0, i32 0
@@ -981,7 +981,7 @@ entry:
 
 define <2 x float> @test_vld1_lane_f32(float* %a, <2 x float> %b) {
 ; CHECK-LABEL: test_vld1_lane_f32
-; CHECK: ld1 {{{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: ld1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %0 = load float* %a, align 4
   %vld1_lane = insertelement <2 x float> %b, float %0, i32 1
@@ -990,7 +990,7 @@ entry:
 
 define <1 x double> @test_vld1_lane_f64(double* %a, <1 x double> %b) {
 ; CHECK-LABEL: test_vld1_lane_f64
-; CHECK: ld1r {{{v[0-9]+}}.1d}, [x0]
+; CHECK: ld1r { {{v[0-9]+}}.1d }, [x0]
 entry:
   %0 = load double* %a, align 8
   %vld1_lane = insertelement <1 x double> undef, double %0, i32 0
@@ -999,7 +999,7 @@ entry:
 
 define %struct.int16x8x2_t @test_vld2q_lane_s16(i16* %a, [2 x <8 x i16>] %b.coerce) {
 ; CHECK-LABEL: test_vld2q_lane_s16
-; CHECK: ld2 {{{v[0-9]+}}.h, {{v[0-9]+}}.h}[{{[0-9]+}}], [x0]
+; CHECK: ld2 { {{v[0-9]+}}.h, {{v[0-9]+}}.h }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [2 x <8 x i16>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [2 x <8 x i16>] %b.coerce, 1
@@ -1014,7 +1014,7 @@ entry:
 
 define %struct.int32x4x2_t @test_vld2q_lane_s32(i32* %a, [2 x <4 x i32>] %b.coerce) {
 ; CHECK-LABEL: test_vld2q_lane_s32
-; CHECK: ld2 {{{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: ld2 { {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %b.coerce, 1
@@ -1029,7 +1029,7 @@ entry:
 
 define %struct.int64x2x2_t @test_vld2q_lane_s64(i64* %a, [2 x <2 x i64>] %b.coerce) {
 ; CHECK-LABEL: test_vld2q_lane_s64
-; CHECK: ld2 {{{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: ld2 { {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [2 x <2 x i64>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [2 x <2 x i64>] %b.coerce, 1
@@ -1044,7 +1044,7 @@ entry:
 
 define %struct.float32x4x2_t @test_vld2q_lane_f32(float* %a, [2 x <4 x float>] %b.coerce) {
 ; CHECK-LABEL: test_vld2q_lane_f32
-; CHECK: ld2 {{{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: ld2 { {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [2 x <4 x float>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [2 x <4 x float>] %b.coerce, 1
@@ -1059,7 +1059,7 @@ entry:
 
 define %struct.float64x2x2_t @test_vld2q_lane_f64(double* %a, [2 x <2 x double>] %b.coerce) {
 ; CHECK-LABEL: test_vld2q_lane_f64
-; CHECK: ld2 {{{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: ld2 { {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [2 x <2 x double>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [2 x <2 x double>] %b.coerce, 1
@@ -1074,7 +1074,7 @@ entry:
 
 define %struct.int8x8x2_t @test_vld2_lane_s8(i8* %a, [2 x <8 x i8>] %b.coerce) {
 ; CHECK-LABEL: test_vld2_lane_s8
-; CHECK: ld2 {{{v[0-9]+}}.b, {{v[0-9]+}}.b}[{{[0-9]+}}], [x0]
+; CHECK: ld2 { {{v[0-9]+}}.b, {{v[0-9]+}}.b }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [2 x <8 x i8>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [2 x <8 x i8>] %b.coerce, 1
@@ -1088,7 +1088,7 @@ entry:
 
 define %struct.int16x4x2_t @test_vld2_lane_s16(i16* %a, [2 x <4 x i16>] %b.coerce) {
 ; CHECK-LABEL: test_vld2_lane_s16
-; CHECK: ld2 {{{v[0-9]+}}.h, {{v[0-9]+}}.h}[{{[0-9]+}}], [x0]
+; CHECK: ld2 { {{v[0-9]+}}.h, {{v[0-9]+}}.h }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [2 x <4 x i16>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [2 x <4 x i16>] %b.coerce, 1
@@ -1103,7 +1103,7 @@ entry:
 
 define %struct.int32x2x2_t @test_vld2_lane_s32(i32* %a, [2 x <2 x i32>] %b.coerce) {
 ; CHECK-LABEL: test_vld2_lane_s32
-; CHECK: ld2 {{{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: ld2 { {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [2 x <2 x i32>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [2 x <2 x i32>] %b.coerce, 1
@@ -1118,7 +1118,7 @@ entry:
 
 define %struct.int64x1x2_t @test_vld2_lane_s64(i64* %a, [2 x <1 x i64>] %b.coerce) {
 ; CHECK-LABEL: test_vld2_lane_s64
-; CHECK: ld2 {{{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: ld2 { {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [2 x <1 x i64>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [2 x <1 x i64>] %b.coerce, 1
@@ -1133,7 +1133,7 @@ entry:
 
 define %struct.float32x2x2_t @test_vld2_lane_f32(float* %a, [2 x <2 x float>] %b.coerce) {
 ; CHECK-LABEL: test_vld2_lane_f32
-; CHECK: ld2 {{{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: ld2 { {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [2 x <2 x float>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [2 x <2 x float>] %b.coerce, 1
@@ -1148,7 +1148,7 @@ entry:
 
 define %struct.float64x1x2_t @test_vld2_lane_f64(double* %a, [2 x <1 x double>] %b.coerce) {
 ; CHECK-LABEL: test_vld2_lane_f64
-; CHECK: ld2 {{{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: ld2 { {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [2 x <1 x double>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [2 x <1 x double>] %b.coerce, 1
@@ -1163,7 +1163,7 @@ entry:
 
 define %struct.int16x8x3_t @test_vld3q_lane_s16(i16* %a, [3 x <8 x i16>] %b.coerce) {
 ; CHECK-LABEL: test_vld3q_lane_s16
-; CHECK: ld3 {{{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h}[{{[0-9]+}}], [x0]
+; CHECK: ld3 { {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [3 x <8 x i16>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [3 x <8 x i16>] %b.coerce, 1
@@ -1181,7 +1181,7 @@ entry:
 
 define %struct.int32x4x3_t @test_vld3q_lane_s32(i32* %a, [3 x <4 x i32>] %b.coerce) {
 ; CHECK-LABEL: test_vld3q_lane_s32
-; CHECK: ld3 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: ld3 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [3 x <4 x i32>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [3 x <4 x i32>] %b.coerce, 1
@@ -1199,7 +1199,7 @@ entry:
 
 define %struct.int64x2x3_t @test_vld3q_lane_s64(i64* %a, [3 x <2 x i64>] %b.coerce) {
 ; CHECK-LABEL: test_vld3q_lane_s64
-; CHECK: ld3 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: ld3 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [3 x <2 x i64>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [3 x <2 x i64>] %b.coerce, 1
@@ -1217,7 +1217,7 @@ entry:
 
 define %struct.float32x4x3_t @test_vld3q_lane_f32(float* %a, [3 x <4 x float>] %b.coerce) {
 ; CHECK-LABEL: test_vld3q_lane_f32
-; CHECK: ld3 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: ld3 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [3 x <4 x float>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [3 x <4 x float>] %b.coerce, 1
@@ -1235,7 +1235,7 @@ entry:
 
 define %struct.float64x2x3_t @test_vld3q_lane_f64(double* %a, [3 x <2 x double>] %b.coerce) {
 ; CHECK-LABEL: test_vld3q_lane_f64
-; CHECK: ld3 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: ld3 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [3 x <2 x double>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [3 x <2 x double>] %b.coerce, 1
@@ -1253,7 +1253,7 @@ entry:
 
 define %struct.int8x8x3_t @test_vld3_lane_s8(i8* %a, [3 x <8 x i8>] %b.coerce) {
 ; CHECK-LABEL: test_vld3_lane_s8
-; CHECK: ld3 {{{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b}[{{[0-9]+}}], [x0]
+; CHECK: ld3 { {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [3 x <8 x i8>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [3 x <8 x i8>] %b.coerce, 1
@@ -1270,7 +1270,7 @@ entry:
 
 define %struct.int16x4x3_t @test_vld3_lane_s16(i16* %a, [3 x <4 x i16>] %b.coerce) {
 ; CHECK-LABEL: test_vld3_lane_s16
-; CHECK: ld3 {{{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h}[{{[0-9]+}}], [x0]
+; CHECK: ld3 { {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [3 x <4 x i16>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [3 x <4 x i16>] %b.coerce, 1
@@ -1288,7 +1288,7 @@ entry:
 
 define %struct.int32x2x3_t @test_vld3_lane_s32(i32* %a, [3 x <2 x i32>] %b.coerce) {
 ; CHECK-LABEL: test_vld3_lane_s32
-; CHECK: ld3 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: ld3 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [3 x <2 x i32>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [3 x <2 x i32>] %b.coerce, 1
@@ -1306,7 +1306,7 @@ entry:
 
 define %struct.int64x1x3_t @test_vld3_lane_s64(i64* %a, [3 x <1 x i64>] %b.coerce) {
 ; CHECK-LABEL: test_vld3_lane_s64
-; CHECK: ld3 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: ld3 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [3 x <1 x i64>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [3 x <1 x i64>] %b.coerce, 1
@@ -1324,7 +1324,7 @@ entry:
 
 define %struct.float32x2x3_t @test_vld3_lane_f32(float* %a, [3 x <2 x float>] %b.coerce) {
 ; CHECK-LABEL: test_vld3_lane_f32
-; CHECK: ld3 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: ld3 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [3 x <2 x float>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [3 x <2 x float>] %b.coerce, 1
@@ -1342,7 +1342,7 @@ entry:
 
 define %struct.float64x1x3_t @test_vld3_lane_f64(double* %a, [3 x <1 x double>] %b.coerce) {
 ; CHECK-LABEL: test_vld3_lane_f64
-; CHECK: ld3 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: ld3 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [3 x <1 x double>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [3 x <1 x double>] %b.coerce, 1
@@ -1360,7 +1360,7 @@ entry:
 
 define %struct.int8x16x4_t @test_vld4q_lane_s8(i8* %a, [4 x <16 x i8>] %b.coerce) {
 ; CHECK-LABEL: test_vld4q_lane_s8
-; CHECK: ld4 {{{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b}[{{[0-9]+}}], [x0]
+; CHECK: ld4 { {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [4 x <16 x i8>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [4 x <16 x i8>] %b.coerce, 1
@@ -1380,7 +1380,7 @@ entry:
 
 define %struct.int16x8x4_t @test_vld4q_lane_s16(i16* %a, [4 x <8 x i16>] %b.coerce) {
 ; CHECK-LABEL: test_vld4q_lane_s16
-; CHECK: ld4 {{{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h}[{{[0-9]+}}], [x0]
+; CHECK: ld4 { {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [4 x <8 x i16>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [4 x <8 x i16>] %b.coerce, 1
@@ -1401,7 +1401,7 @@ entry:
 
 define %struct.int32x4x4_t @test_vld4q_lane_s32(i32* %a, [4 x <4 x i32>] %b.coerce) {
 ; CHECK-LABEL: test_vld4q_lane_s32
-; CHECK: ld4 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: ld4 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [4 x <4 x i32>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [4 x <4 x i32>] %b.coerce, 1
@@ -1422,7 +1422,7 @@ entry:
 
 define %struct.int64x2x4_t @test_vld4q_lane_s64(i64* %a, [4 x <2 x i64>] %b.coerce) {
 ; CHECK-LABEL: test_vld4q_lane_s64
-; CHECK: ld4 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: ld4 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [4 x <2 x i64>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [4 x <2 x i64>] %b.coerce, 1
@@ -1443,7 +1443,7 @@ entry:
 
 define %struct.float32x4x4_t @test_vld4q_lane_f32(float* %a, [4 x <4 x float>] %b.coerce) {
 ; CHECK-LABEL: test_vld4q_lane_f32
-; CHECK: ld4 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: ld4 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [4 x <4 x float>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [4 x <4 x float>] %b.coerce, 1
@@ -1464,7 +1464,7 @@ entry:
 
 define %struct.float64x2x4_t @test_vld4q_lane_f64(double* %a, [4 x <2 x double>] %b.coerce) {
 ; CHECK-LABEL: test_vld4q_lane_f64
-; CHECK: ld4 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: ld4 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [4 x <2 x double>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [4 x <2 x double>] %b.coerce, 1
@@ -1485,7 +1485,7 @@ entry:
 
 define %struct.int8x8x4_t @test_vld4_lane_s8(i8* %a, [4 x <8 x i8>] %b.coerce) {
 ; CHECK-LABEL: test_vld4_lane_s8
-; CHECK: ld4 {{{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b}[{{[0-9]+}}], [x0]
+; CHECK: ld4 { {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [4 x <8 x i8>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [4 x <8 x i8>] %b.coerce, 1
@@ -1505,7 +1505,7 @@ entry:
 
 define %struct.int16x4x4_t @test_vld4_lane_s16(i16* %a, [4 x <4 x i16>] %b.coerce) {
 ; CHECK-LABEL: test_vld4_lane_s16
-; CHECK: ld4 {{{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h}[{{[0-9]+}}], [x0]
+; CHECK: ld4 { {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [4 x <4 x i16>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [4 x <4 x i16>] %b.coerce, 1
@@ -1526,7 +1526,7 @@ entry:
 
 define %struct.int32x2x4_t @test_vld4_lane_s32(i32* %a, [4 x <2 x i32>] %b.coerce) {
 ; CHECK-LABEL: test_vld4_lane_s32
-; CHECK: ld4 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: ld4 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [4 x <2 x i32>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [4 x <2 x i32>] %b.coerce, 1
@@ -1547,7 +1547,7 @@ entry:
 
 define %struct.int64x1x4_t @test_vld4_lane_s64(i64* %a, [4 x <1 x i64>] %b.coerce) {
 ; CHECK-LABEL: test_vld4_lane_s64
-; CHECK: ld4 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: ld4 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [4 x <1 x i64>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [4 x <1 x i64>] %b.coerce, 1
@@ -1568,7 +1568,7 @@ entry:
 
 define %struct.float32x2x4_t @test_vld4_lane_f32(float* %a, [4 x <2 x float>] %b.coerce) {
 ; CHECK-LABEL: test_vld4_lane_f32
-; CHECK: ld4 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: ld4 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [4 x <2 x float>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [4 x <2 x float>] %b.coerce, 1
@@ -1589,7 +1589,7 @@ entry:
 
 define %struct.float64x1x4_t @test_vld4_lane_f64(double* %a, [4 x <1 x double>] %b.coerce) {
 ; CHECK-LABEL: test_vld4_lane_f64
-; CHECK: ld4 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: ld4 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [4 x <1 x double>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [4 x <1 x double>] %b.coerce, 1
@@ -1610,7 +1610,7 @@ entry:
 
 define void @test_vst1q_lane_s8(i8* %a, <16 x i8> %b) {
 ; CHECK-LABEL: test_vst1q_lane_s8
-; CHECK: st1 {{{v[0-9]+}}.b}[{{[0-9]+}}], [x0]
+; CHECK: st1 { {{v[0-9]+}}.b }[{{[0-9]+}}], [x0]
 entry:
   %0 = extractelement <16 x i8> %b, i32 15
   store i8 %0, i8* %a, align 1
@@ -1619,7 +1619,7 @@ entry:
 
 define void @test_vst1q_lane_s16(i16* %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vst1q_lane_s16
-; CHECK: st1 {{{v[0-9]+}}.h}[{{[0-9]+}}], [x0]
+; CHECK: st1 { {{v[0-9]+}}.h }[{{[0-9]+}}], [x0]
 entry:
   %0 = extractelement <8 x i16> %b, i32 7
   store i16 %0, i16* %a, align 2
@@ -1628,7 +1628,7 @@ entry:
 
 define void @test_vst1q_lane_s32(i32* %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vst1q_lane_s32
-; CHECK: st1 {{{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: st1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %0 = extractelement <4 x i32> %b, i32 3
   store i32 %0, i32* %a, align 4
@@ -1637,7 +1637,7 @@ entry:
 
 define void @test_vst1q_lane_s64(i64* %a, <2 x i64> %b) {
 ; CHECK-LABEL: test_vst1q_lane_s64
-; CHECK: st1 {{{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: st1 { {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %0 = extractelement <2 x i64> %b, i32 1
   store i64 %0, i64* %a, align 8
@@ -1646,7 +1646,7 @@ entry:
 
 define void @test_vst1q_lane_f32(float* %a, <4 x float> %b) {
 ; CHECK-LABEL: test_vst1q_lane_f32
-; CHECK: st1 {{{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: st1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %0 = extractelement <4 x float> %b, i32 3
   store float %0, float* %a, align 4
@@ -1655,7 +1655,7 @@ entry:
 
 define void @test_vst1q_lane_f64(double* %a, <2 x double> %b) {
 ; CHECK-LABEL: test_vst1q_lane_f64
-; CHECK: st1 {{{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: st1 { {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %0 = extractelement <2 x double> %b, i32 1
   store double %0, double* %a, align 8
@@ -1664,7 +1664,7 @@ entry:
 
 define void @test_vst1_lane_s8(i8* %a, <8 x i8> %b) {
 ; CHECK-LABEL: test_vst1_lane_s8
-; CHECK: st1 {{{v[0-9]+}}.b}[{{[0-9]+}}], [x0]
+; CHECK: st1 { {{v[0-9]+}}.b }[{{[0-9]+}}], [x0]
 entry:
   %0 = extractelement <8 x i8> %b, i32 7
   store i8 %0, i8* %a, align 1
@@ -1673,7 +1673,7 @@ entry:
 
 define void @test_vst1_lane_s16(i16* %a, <4 x i16> %b) {
 ; CHECK-LABEL: test_vst1_lane_s16
-; CHECK: st1 {{{v[0-9]+}}.h}[{{[0-9]+}}], [x0]
+; CHECK: st1 { {{v[0-9]+}}.h }[{{[0-9]+}}], [x0]
 entry:
   %0 = extractelement <4 x i16> %b, i32 3
   store i16 %0, i16* %a, align 2
@@ -1682,7 +1682,7 @@ entry:
 
 define void @test_vst1_lane_s32(i32* %a, <2 x i32> %b) {
 ; CHECK-LABEL: test_vst1_lane_s32
-; CHECK: st1 {{{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: st1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %0 = extractelement <2 x i32> %b, i32 1
   store i32 %0, i32* %a, align 4
@@ -1691,7 +1691,7 @@ entry:
 
 define void @test_vst1_lane_s64(i64* %a, <1 x i64> %b) {
 ; CHECK-LABEL: test_vst1_lane_s64
-; CHECK: st1 {{{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: st1 { {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %0 = extractelement <1 x i64> %b, i32 0
   store i64 %0, i64* %a, align 8
@@ -1700,7 +1700,7 @@ entry:
 
 define void @test_vst1_lane_f32(float* %a, <2 x float> %b) {
 ; CHECK-LABEL: test_vst1_lane_f32
-; CHECK: st1 {{{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: st1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %0 = extractelement <2 x float> %b, i32 1
   store float %0, float* %a, align 4
@@ -1709,7 +1709,7 @@ entry:
 
 define void @test_vst1_lane_f64(double* %a, <1 x double> %b) {
 ; CHECK-LABEL: test_vst1_lane_f64
-; CHECK: st1 {{{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: st1 { {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %0 = extractelement <1 x double> %b, i32 0
   store double %0, double* %a, align 8
@@ -1718,7 +1718,7 @@ entry:
 
 define void @test_vst2q_lane_s8(i8* %a, [2 x <16 x i8>] %b.coerce) {
 ; CHECK-LABEL: test_vst2q_lane_s8
-; CHECK: st2 {{{v[0-9]+}}.b, {{v[0-9]+}}.b}[{{[0-9]+}}], [x0]
+; CHECK: st2 { {{v[0-9]+}}.b, {{v[0-9]+}}.b }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [2 x <16 x i8>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [2 x <16 x i8>] %b.coerce, 1
@@ -1728,7 +1728,7 @@ entry:
 
 define void @test_vst2q_lane_s16(i16* %a, [2 x <8 x i16>] %b.coerce) {
 ; CHECK-LABEL: test_vst2q_lane_s16
-; CHECK: st2 {{{v[0-9]+}}.h, {{v[0-9]+}}.h}[{{[0-9]+}}], [x0]
+; CHECK: st2 { {{v[0-9]+}}.h, {{v[0-9]+}}.h }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [2 x <8 x i16>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [2 x <8 x i16>] %b.coerce, 1
@@ -1739,7 +1739,7 @@ entry:
 
 define void @test_vst2q_lane_s32(i32* %a, [2 x <4 x i32>] %b.coerce) {
 ; CHECK-LABEL: test_vst2q_lane_s32
-; CHECK: st2 {{{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: st2 { {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %b.coerce, 1
@@ -1750,7 +1750,7 @@ entry:
 
 define void @test_vst2q_lane_s64(i64* %a, [2 x <2 x i64>] %b.coerce) {
 ; CHECK-LABEL: test_vst2q_lane_s64
-; CHECK: st2 {{{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: st2 { {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [2 x <2 x i64>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [2 x <2 x i64>] %b.coerce, 1
@@ -1761,7 +1761,7 @@ entry:
 
 define void @test_vst2q_lane_f32(float* %a, [2 x <4 x float>] %b.coerce) {
 ; CHECK-LABEL: test_vst2q_lane_f32
-; CHECK: st2 {{{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: st2 { {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [2 x <4 x float>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [2 x <4 x float>] %b.coerce, 1
@@ -1772,7 +1772,7 @@ entry:
 
 define void @test_vst2q_lane_f64(double* %a, [2 x <2 x double>] %b.coerce) {
 ; CHECK-LABEL: test_vst2q_lane_f64
-; CHECK: st2 {{{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: st2 { {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [2 x <2 x double>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [2 x <2 x double>] %b.coerce, 1
@@ -1783,7 +1783,7 @@ entry:
 
 define void @test_vst2_lane_s8(i8* %a, [2 x <8 x i8>] %b.coerce) {
 ; CHECK-LABEL: test_vst2_lane_s8
-; CHECK: st2 {{{v[0-9]+}}.b, {{v[0-9]+}}.b}[{{[0-9]+}}], [x0]
+; CHECK: st2 { {{v[0-9]+}}.b, {{v[0-9]+}}.b }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [2 x <8 x i8>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [2 x <8 x i8>] %b.coerce, 1
@@ -1793,7 +1793,7 @@ entry:
 
 define void @test_vst2_lane_s16(i16* %a, [2 x <4 x i16>] %b.coerce) {
 ; CHECK-LABEL: test_vst2_lane_s16
-; CHECK: st2 {{{v[0-9]+}}.h, {{v[0-9]+}}.h}[{{[0-9]+}}], [x0]
+; CHECK: st2 { {{v[0-9]+}}.h, {{v[0-9]+}}.h }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [2 x <4 x i16>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [2 x <4 x i16>] %b.coerce, 1
@@ -1804,7 +1804,7 @@ entry:
 
 define void @test_vst2_lane_s32(i32* %a, [2 x <2 x i32>] %b.coerce) {
 ; CHECK-LABEL: test_vst2_lane_s32
-; CHECK: st2 {{{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: st2 { {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [2 x <2 x i32>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [2 x <2 x i32>] %b.coerce, 1
@@ -1815,7 +1815,7 @@ entry:
 
 define void @test_vst2_lane_s64(i64* %a, [2 x <1 x i64>] %b.coerce) {
 ; CHECK-LABEL: test_vst2_lane_s64
-; CHECK: st2 {{{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: st2 { {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [2 x <1 x i64>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [2 x <1 x i64>] %b.coerce, 1
@@ -1826,7 +1826,7 @@ entry:
 
 define void @test_vst2_lane_f32(float* %a, [2 x <2 x float>] %b.coerce) {
 ; CHECK-LABEL: test_vst2_lane_f32
-; CHECK: st2 {{{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: st2 { {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [2 x <2 x float>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [2 x <2 x float>] %b.coerce, 1
@@ -1837,7 +1837,7 @@ entry:
 
 define void @test_vst2_lane_f64(double* %a, [2 x <1 x double>] %b.coerce) {
 ; CHECK-LABEL: test_vst2_lane_f64
-; CHECK: st2 {{{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: st2 { {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [2 x <1 x double>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [2 x <1 x double>] %b.coerce, 1
@@ -1848,7 +1848,7 @@ entry:
 
 define void @test_vst3q_lane_s8(i8* %a, [3 x <16 x i8>] %b.coerce) {
 ; CHECK-LABEL: test_vst3q_lane_s8
-; CHECK: st3 {{{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b}[{{[0-9]+}}], [x0]
+; CHECK: st3 { {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [3 x <16 x i8>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [3 x <16 x i8>] %b.coerce, 1
@@ -1859,7 +1859,7 @@ entry:
 
 define void @test_vst3q_lane_s16(i16* %a, [3 x <8 x i16>] %b.coerce) {
 ; CHECK-LABEL: test_vst3q_lane_s16
-; CHECK: st3 {{{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h}[{{[0-9]+}}], [x0]
+; CHECK: st3 { {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [3 x <8 x i16>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [3 x <8 x i16>] %b.coerce, 1
@@ -1871,7 +1871,7 @@ entry:
 
 define void @test_vst3q_lane_s32(i32* %a, [3 x <4 x i32>] %b.coerce) {
 ; CHECK-LABEL: test_vst3q_lane_s32
-; CHECK: st3 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: st3 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [3 x <4 x i32>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [3 x <4 x i32>] %b.coerce, 1
@@ -1883,7 +1883,7 @@ entry:
 
 define void @test_vst3q_lane_s64(i64* %a, [3 x <2 x i64>] %b.coerce) {
 ; CHECK-LABEL: test_vst3q_lane_s64
-; CHECK: st3 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: st3 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [3 x <2 x i64>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [3 x <2 x i64>] %b.coerce, 1
@@ -1895,7 +1895,7 @@ entry:
 
 define void @test_vst3q_lane_f32(float* %a, [3 x <4 x float>] %b.coerce) {
 ; CHECK-LABEL: test_vst3q_lane_f32
-; CHECK: st3 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: st3 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [3 x <4 x float>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [3 x <4 x float>] %b.coerce, 1
@@ -1907,7 +1907,7 @@ entry:
 
 define void @test_vst3q_lane_f64(double* %a, [3 x <2 x double>] %b.coerce) {
 ; CHECK-LABEL: test_vst3q_lane_f64
-; CHECK: st3 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: st3 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [3 x <2 x double>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [3 x <2 x double>] %b.coerce, 1
@@ -1919,7 +1919,7 @@ entry:
 
 define void @test_vst3_lane_s8(i8* %a, [3 x <8 x i8>] %b.coerce) {
 ; CHECK-LABEL: test_vst3_lane_s8
-; CHECK: st3 {{{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b}[{{[0-9]+}}], [x0]
+; CHECK: st3 { {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [3 x <8 x i8>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [3 x <8 x i8>] %b.coerce, 1
@@ -1930,7 +1930,7 @@ entry:
 
 define void @test_vst3_lane_s16(i16* %a, [3 x <4 x i16>] %b.coerce) {
 ; CHECK-LABEL: test_vst3_lane_s16
-; CHECK: st3 {{{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h}[{{[0-9]+}}], [x0]
+; CHECK: st3 { {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [3 x <4 x i16>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [3 x <4 x i16>] %b.coerce, 1
@@ -1942,7 +1942,7 @@ entry:
 
 define void @test_vst3_lane_s32(i32* %a, [3 x <2 x i32>] %b.coerce) {
 ; CHECK-LABEL: test_vst3_lane_s32
-; CHECK: st3 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: st3 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [3 x <2 x i32>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [3 x <2 x i32>] %b.coerce, 1
@@ -1954,7 +1954,7 @@ entry:
 
 define void @test_vst3_lane_s64(i64* %a, [3 x <1 x i64>] %b.coerce) {
 ; CHECK-LABEL: test_vst3_lane_s64
-; CHECK: st3 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: st3 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [3 x <1 x i64>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [3 x <1 x i64>] %b.coerce, 1
@@ -1966,7 +1966,7 @@ entry:
 
 define void @test_vst3_lane_f32(float* %a, [3 x <2 x float>] %b.coerce) {
 ; CHECK-LABEL: test_vst3_lane_f32
-; CHECK: st3 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: st3 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [3 x <2 x float>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [3 x <2 x float>] %b.coerce, 1
@@ -1978,7 +1978,7 @@ entry:
 
 define void @test_vst3_lane_f64(double* %a, [3 x <1 x double>] %b.coerce) {
 ; CHECK-LABEL: test_vst3_lane_f64
-; CHECK: st3 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: st3 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [3 x <1 x double>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [3 x <1 x double>] %b.coerce, 1
@@ -1990,7 +1990,7 @@ entry:
 
 define void @test_vst4q_lane_s8(i16* %a, [4 x <16 x i8>] %b.coerce) {
 ; CHECK-LABEL: test_vst4q_lane_s8
-; CHECK: st4 {{{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b}[{{[0-9]+}}], [x0]
+; CHECK: st4 { {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [4 x <16 x i8>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [4 x <16 x i8>] %b.coerce, 1
@@ -2003,7 +2003,7 @@ entry:
 
 define void @test_vst4q_lane_s16(i16* %a, [4 x <8 x i16>] %b.coerce) {
 ; CHECK-LABEL: test_vst4q_lane_s16
-; CHECK: st4 {{{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h}[{{[0-9]+}}], [x0]
+; CHECK: st4 { {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [4 x <8 x i16>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [4 x <8 x i16>] %b.coerce, 1
@@ -2016,7 +2016,7 @@ entry:
 
 define void @test_vst4q_lane_s32(i32* %a, [4 x <4 x i32>] %b.coerce) {
 ; CHECK-LABEL: test_vst4q_lane_s32
-; CHECK: st4 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: st4 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [4 x <4 x i32>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [4 x <4 x i32>] %b.coerce, 1
@@ -2029,7 +2029,7 @@ entry:
 
 define void @test_vst4q_lane_s64(i64* %a, [4 x <2 x i64>] %b.coerce) {
 ; CHECK-LABEL: test_vst4q_lane_s64
-; CHECK: st4 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: st4 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [4 x <2 x i64>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [4 x <2 x i64>] %b.coerce, 1
@@ -2042,7 +2042,7 @@ entry:
 
 define void @test_vst4q_lane_f32(float* %a, [4 x <4 x float>] %b.coerce) {
 ; CHECK-LABEL: test_vst4q_lane_f32
-; CHECK: st4 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: st4 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [4 x <4 x float>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [4 x <4 x float>] %b.coerce, 1
@@ -2055,7 +2055,7 @@ entry:
 
 define void @test_vst4q_lane_f64(double* %a, [4 x <2 x double>] %b.coerce) {
 ; CHECK-LABEL: test_vst4q_lane_f64
-; CHECK: st4 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: st4 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [4 x <2 x double>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [4 x <2 x double>] %b.coerce, 1
@@ -2068,7 +2068,7 @@ entry:
 
 define void @test_vst4_lane_s8(i8* %a, [4 x <8 x i8>] %b.coerce) {
 ; CHECK-LABEL: test_vst4_lane_s8
-; CHECK: st4 {{{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b}[{{[0-9]+}}], [x0]
+; CHECK: st4 { {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [4 x <8 x i8>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [4 x <8 x i8>] %b.coerce, 1
@@ -2080,7 +2080,7 @@ entry:
 
 define void @test_vst4_lane_s16(i16* %a, [4 x <4 x i16>] %b.coerce) {
 ; CHECK-LABEL: test_vst4_lane_s16
-; CHECK: st4 {{{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h}[{{[0-9]+}}], [x0]
+; CHECK: st4 { {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [4 x <4 x i16>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [4 x <4 x i16>] %b.coerce, 1
@@ -2093,7 +2093,7 @@ entry:
 
 define void @test_vst4_lane_s32(i32* %a, [4 x <2 x i32>] %b.coerce) {
 ; CHECK-LABEL: test_vst4_lane_s32
-; CHECK: st4 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: st4 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [4 x <2 x i32>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [4 x <2 x i32>] %b.coerce, 1
@@ -2106,7 +2106,7 @@ entry:
 
 define void @test_vst4_lane_s64(i64* %a, [4 x <1 x i64>] %b.coerce) {
 ; CHECK-LABEL: test_vst4_lane_s64
-; CHECK: st4 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: st4 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [4 x <1 x i64>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [4 x <1 x i64>] %b.coerce, 1
@@ -2119,7 +2119,7 @@ entry:
 
 define void @test_vst4_lane_f32(float* %a, [4 x <2 x float>] %b.coerce) {
 ; CHECK-LABEL: test_vst4_lane_f32
-; CHECK: st4 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0]
+; CHECK: st4 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [4 x <2 x float>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [4 x <2 x float>] %b.coerce, 1
@@ -2132,7 +2132,7 @@ entry:
 
 define void @test_vst4_lane_f64(double* %a, [4 x <1 x double>] %b.coerce) {
 ; CHECK-LABEL: test_vst4_lane_f64
-; CHECK: st4 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0]
+; CHECK: st4 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0]
 entry:
   %b.coerce.fca.0.extract = extractvalue [4 x <1 x double>] %b.coerce, 0
   %b.coerce.fca.1.extract = extractvalue [4 x <1 x double>] %b.coerce, 1
@@ -2224,7 +2224,7 @@ declare void @llvm.arm.neon.vst4lane.v1f64(i8*, <1 x double>, <1 x double>, <1 x
 
 define %struct.int8x16x2_t @test_vld2q_lane_s8(i8* readonly %ptr, [2 x <16 x i8>] %src.coerce) {
 ; CHECK-LABEL: test_vld2q_lane_s8
-; CHECK: ld2 {{{v[0-9]+}}.b, {{v[0-9]+}}.b}[15], [x0]
+; CHECK: ld2 { {{v[0-9]+}}.b, {{v[0-9]+}}.b }[15], [x0]
 entry:
   %src.coerce.fca.0.extract = extractvalue [2 x <16 x i8>] %src.coerce, 0
   %src.coerce.fca.1.extract = extractvalue [2 x <16 x i8>] %src.coerce, 1
@@ -2238,7 +2238,7 @@ entry:
 
 define %struct.uint8x16x2_t @test_vld2q_lane_u8(i8* readonly %ptr, [2 x <16 x i8>] %src.coerce) {
 ; CHECK-LABEL: test_vld2q_lane_u8
-; CHECK: ld2 {{{v[0-9]+}}.b, {{v[0-9]+}}.b}[15], [x0]
+; CHECK: ld2 { {{v[0-9]+}}.b, {{v[0-9]+}}.b }[15], [x0]
 entry:
   %src.coerce.fca.0.extract = extractvalue [2 x <16 x i8>] %src.coerce, 0
   %src.coerce.fca.1.extract = extractvalue [2 x <16 x i8>] %src.coerce, 1
@@ -2252,7 +2252,7 @@ entry:
 
 define %struct.poly8x16x2_t @test_vld2q_lane_p8(i8* readonly %ptr, [2 x <16 x i8>] %src.coerce) {
 ; CHECK-LABEL: test_vld2q_lane_p8
-; CHECK: ld2 {{{v[0-9]+}}.b, {{v[0-9]+}}.b}[15], [x0]
+; CHECK: ld2 { {{v[0-9]+}}.b, {{v[0-9]+}}.b }[15], [x0]
 entry:
   %src.coerce.fca.0.extract = extractvalue [2 x <16 x i8>] %src.coerce, 0
   %src.coerce.fca.1.extract = extractvalue [2 x <16 x i8>] %src.coerce, 1
@@ -2266,7 +2266,7 @@ entry:
 
 define %struct.int8x16x3_t @test_vld3q_lane_s8(i8* readonly %ptr, [3 x <16 x i8>] %src.coerce) {
 ; CHECK-LABEL: test_vld3q_lane_s8
-; CHECK: ld3 {{{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b}[15], [x0]
+; CHECK: ld3 { {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b }[15], [x0]
 entry:
   %src.coerce.fca.0.extract = extractvalue [3 x <16 x i8>] %src.coerce, 0
   %src.coerce.fca.1.extract = extractvalue [3 x <16 x i8>] %src.coerce, 1
@@ -2283,7 +2283,7 @@ entry:
 
 define %struct.uint8x16x3_t @test_vld3q_lane_u8(i8* readonly %ptr, [3 x <16 x i8>] %src.coerce) {
 ; CHECK-LABEL: test_vld3q_lane_u8
-; CHECK: ld3 {{{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b}[15], [x0]
+; CHECK: ld3 { {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b }[15], [x0]
 entry:
   %src.coerce.fca.0.extract = extractvalue [3 x <16 x i8>] %src.coerce, 0
   %src.coerce.fca.1.extract = extractvalue [3 x <16 x i8>] %src.coerce, 1