[AArch64][FastISel] Fix integer extend optimization.

[oota-llvm.git] / test / CodeGen / AArch64 / neon-truncStore-extLoad.ll

diff --git a/test/CodeGen/AArch64/neon-truncStore-extLoad.ll b/test/CodeGen/AArch64/neon-truncStore-extLoad.ll
index dbaccacdf55420b5bd4711a369cd5f1a0563a479..0d5ebb324ecb6aae98a80f1e7a0c9db0ebddc4ce 100644 (file)
--- a/test/CodeGen/AArch64/neon-truncStore-extLoad.ll
+++ b/test/CodeGen/AArch64/neon-truncStore-extLoad.ll
@@ -1,5 +1,4 @@
 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
-; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s
 
 ; A vector TruncStore can not be selected.
 ; Test a trunc IR and a vector store IR can be selected correctly.
@@ -35,7 +34,7 @@ define void @truncStore.v8i16(<8 x i16> %a, <8 x i8>* %result) {
 define <4 x i32> @loadSExt.v4i8(<4 x i8>* %ref) {
 ; CHECK-LABEL: loadSExt.v4i8:
 ; CHECK: ldrsb
-  %a = load <4 x i8>* %ref
+  %a = load <4 x i8>, <4 x i8>* %ref
   %conv = sext <4 x i8> %a to <4 x i32>
   ret <4 x i32> %conv
 }
@@ -43,7 +42,7 @@ define <4 x i32> @loadSExt.v4i8(<4 x i8>* %ref) {
 define <4 x i32> @loadZExt.v4i8(<4 x i8>* %ref) {
 ; CHECK-LABEL: loadZExt.v4i8:
 ; CHECK: ldrb
-  %a = load <4 x i8>* %ref
+  %a = load <4 x i8>, <4 x i8>* %ref
   %conv = zext <4 x i8> %a to <4 x i32>
   ret <4 x i32> %conv
 }
@@ -51,7 +50,7 @@ define <4 x i32> @loadZExt.v4i8(<4 x i8>* %ref) {
 define i32 @loadExt.i32(<4 x i8>* %ref) {
 ; CHECK-LABEL: loadExt.i32:
 ; CHECK: ldrb
-  %a = load <4 x i8>* %ref
+  %a = load <4 x i8>, <4 x i8>* %ref
   %vecext = extractelement <4 x i8> %a, i32 0
   %conv = zext i8 %vecext to i32
   ret i32 %conv