AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.

[oota-llvm.git] / test / CodeGen / AArch64 / regress-tblgen-chains.ll

diff --git a/test/CodeGen/AArch64/regress-tblgen-chains.ll b/test/CodeGen/AArch64/regress-tblgen-chains.ll
index 1f8ad4503c41722355524bf119d9477a25f59015..55c3bcdcdd46223d67e80434d2a994ebcce363db 100644 (file)
--- a/test/CodeGen/AArch64/regress-tblgen-chains.ll
+++ b/test/CodeGen/AArch64/regress-tblgen-chains.ll
@@ -1,4 +1,3 @@
-; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s --check-prefix CHECK-AARCH64
 ; RUN: llc -verify-machineinstrs -mtriple=arm64-apple-ios7.0 -o - %s | FileCheck %s --check-prefix CHECK-ARM64
 
 ; When generating DAG selection tables, TableGen used to only flag an
@@ -13,7 +12,6 @@
 declare void @bar(i8*)
 
 define i64 @test_chains() {
-; CHECK-AARCH64-LABEL: test_chains:
 ; CHECK-ARM64-LABEL: test_chains:
 
   %locvar = alloca i8
@@ -26,10 +24,6 @@ define i64 @test_chains() {
   %inc.3 = add i64 %inc.2, 1
   %inc.4 = trunc i64 %inc.3 to i8
   store i8 %inc.4, i8* %locvar
-; CHECK-AARCH64: ldrb {{w[0-9]+}}, [sp, [[LOCADDR:#[0-9]+]]]
-; CHECK-AARCH64: add {{w[0-9]+}}, {{w[0-9]+}}, #1
-; CHECK-AARCH64: strb {{w[0-9]+}}, [sp, [[LOCADDR]]]
-; CHECK-AARCH64: ldrb {{w[0-9]+}}, [sp, [[LOCADDR]]]
 
 ; CHECK-ARM64: ldurb {{w[0-9]+}}, [x29, [[LOCADDR:#-?[0-9]+]]]
 ; CHECK-ARM64: add {{w[0-9]+}}, {{w[0-9]+}}, #1
@@ -39,6 +33,5 @@ define i64 @test_chains() {
   %ret.1 = load i8* %locvar
   %ret.2 = zext i8 %ret.1 to i64
   ret i64 %ret.2
-; CHECK-AARCH64: ret
 ; CHECK-ARM64: ret
 }