R600: Improve texture handling

[oota-llvm.git] / test / CodeGen / ARM / 2007-01-19-InfiniteLoop.ll

diff --git a/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll b/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
index 0dbf79562d965c541313d8165ffe3cc81cddef25..0bfe33175196a738155d694cd2ce7de79aaad87d 100644 (file)
--- a/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
+++ b/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
@@ -1,11 +1,16 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6,+vfp2
+; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+v6,+vfp2 | FileCheck %s
 
 @quant_coef = external global [6 x [4 x [4 x i32]]]            ; <[6 x [4 x [4 x i32]]]*> [#uses=1]
 @dequant_coef = external global [6 x [4 x [4 x i32]]]          ; <[6 x [4 x [4 x i32]]]*> [#uses=1]
 @A = external global [4 x [4 x i32]]           ; <[4 x [4 x i32]]*> [#uses=1]
 
+; CHECK: dct_luma_sp:
 define fastcc i32 @dct_luma_sp(i32 %block_x, i32 %block_y, i32* %coeff_cost) {
 entry:
+; Make sure to use base-updating stores for saving callee-saved registers.
+; CHECK: push
+; CHECK-NOT: sub sp
+; CHECK: push 
        %predicted_block = alloca [4 x [4 x i32]], align 4              ; <[4 x [4 x i32]]*> [#uses=1]
        br label %cond_next489
 
@@ -19,13 +24,13 @@ cond_next489:               ; preds = %cond_false, %bb471
        %tmp502 = load i32* null                ; <i32> [#uses=1]
        %tmp542 = getelementptr [6 x [4 x [4 x i32]]]* @quant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7            ; <i32*> [#uses=1]
        %tmp543 = load i32* %tmp542             ; <i32> [#uses=1]
-       %tmp548 = ashr i32 0, i8 0              ; <i32> [#uses=3]
+       %tmp548 = ashr i32 0, 0         ; <i32> [#uses=3]
        %tmp561 = sub i32 0, %tmp496            ; <i32> [#uses=3]
        %abscond563 = icmp sgt i32 %tmp561, -1          ; <i1> [#uses=1]
        %abs564 = select i1 %abscond563, i32 %tmp561, i32 0             ; <i32> [#uses=1]
        %tmp572 = mul i32 %abs564, %tmp543              ; <i32> [#uses=1]
        %tmp574 = add i32 %tmp572, 0            ; <i32> [#uses=1]
-       %tmp576 = ashr i32 %tmp574, i8 0                ; <i32> [#uses=7]
+       %tmp576 = ashr i32 %tmp574, 0           ; <i32> [#uses=7]
        %tmp579 = icmp eq i32 %tmp548, %tmp576          ; <i1> [#uses=1]
        br i1 %tmp579, label %bb712, label %cond_next589
 
@@ -34,20 +39,20 @@ cond_next589:               ; preds = %cond_next489
        %tmp606 = load i32* %tmp605             ; <i32> [#uses=1]
        %tmp612 = load i32* null                ; <i32> [#uses=1]
        %tmp629 = load i32* null                ; <i32> [#uses=1]
-       %tmp629 = sitofp i32 %tmp629 to double          ; <double> [#uses=1]
-       %tmp631 = mul double %tmp629, 0.000000e+00              ; <double> [#uses=1]
-       %tmp632 = add double 0.000000e+00, %tmp631              ; <double> [#uses=1]
+       %tmp629a = sitofp i32 %tmp629 to double         ; <double> [#uses=1]
+       %tmp631 = fmul double %tmp629a, 0.000000e+00            ; <double> [#uses=1]
+       %tmp632 = fadd double 0.000000e+00, %tmp631             ; <double> [#uses=1]
        %tmp642 = call fastcc i32 @sign( i32 %tmp576, i32 %tmp561 )             ; <i32> [#uses=1]
        %tmp650 = mul i32 %tmp606, %tmp642              ; <i32> [#uses=1]
        %tmp656 = mul i32 %tmp650, %tmp612              ; <i32> [#uses=1]
-       %tmp658 = shl i32 %tmp656, i8 0         ; <i32> [#uses=1]
-       %tmp659 = ashr i32 %tmp658, i8 6                ; <i32> [#uses=1]
+       %tmp658 = shl i32 %tmp656, 0            ; <i32> [#uses=1]
+       %tmp659 = ashr i32 %tmp658, 6           ; <i32> [#uses=1]
        %tmp660 = sub i32 0, %tmp659            ; <i32> [#uses=1]
        %tmp666 = sub i32 %tmp660, %tmp496              ; <i32> [#uses=1]
-       %tmp666 = sitofp i32 %tmp666 to double          ; <double> [#uses=2]
+       %tmp667 = sitofp i32 %tmp666 to double          ; <double> [#uses=2]
        call void @levrun_linfo_inter( i32 %tmp576, i32 0, i32* null, i32* null )
-       %tmp671 = mul double %tmp666, %tmp666           ; <double> [#uses=1]
-       %tmp675 = add double %tmp671, 0.000000e+00              ; <double> [#uses=1]
+       %tmp671 = fmul double %tmp667, %tmp667          ; <double> [#uses=1]
+       %tmp675 = fadd double %tmp671, 0.000000e+00             ; <double> [#uses=1]
        %tmp678 = fcmp oeq double %tmp632, %tmp675              ; <i1> [#uses=1]
        br i1 %tmp678, label %cond_true679, label %cond_false693
 
@@ -85,8 +90,8 @@ cond_true740:         ; preds = %bb737
        %tmp786 = load i32* %tmp785             ; <i32> [#uses=1]
        %tmp781 = mul i32 %tmp780, %tmp761              ; <i32> [#uses=1]
        %tmp787 = mul i32 %tmp781, %tmp786              ; <i32> [#uses=1]
-       %tmp789 = shl i32 %tmp787, i8 0         ; <i32> [#uses=1]
-       %tmp790 = ashr i32 %tmp789, i8 6                ; <i32> [#uses=1]
+       %tmp789 = shl i32 %tmp787, 0            ; <i32> [#uses=1]
+       %tmp790 = ashr i32 %tmp789, 6           ; <i32> [#uses=1]
        br label %cond_next791
 
 cond_next791:          ; preds = %cond_true740, %bb737