Generate FMINNAN/FMINNUM/FMAXNAN/FMAXNUM from SDAGBuilder.

[oota-llvm.git] / test / CodeGen / ARM / 2009-07-22-SchedulerAssert.ll

diff --git a/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll b/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll
index 24f499036ce428306404d1082b29b48059974ff1..156fd8843bcf686d23d9bed7dc6c0064daab0276 100644 (file)
--- a/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll
+++ b/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm
+; RUN: llc -mtriple=arm-eabi %s -o /dev/null
 
        %struct.cli_ac_alt = type { i8, i8*, i16, i16, %struct.cli_ac_alt* }
        %struct.cli_ac_node = type { i8, i8, %struct.cli_ac_patt*, %struct.cli_ac_node**, %struct.cli_ac_node* }
@@ -6,7 +6,7 @@
        %struct.cli_bm_patt = type { i8*, i8*, i16, i16, i8*, i8*, i8, %struct.cli_bm_patt*, i16 }
        %struct.cli_matcher = type { i16, i8, i8*, %struct.cli_bm_patt**, i32*, i32, i8, i8, %struct.cli_ac_node*, %struct.cli_ac_node**, %struct.cli_ac_patt**, i32, i32, i32 }
 
-define arm_apcscc i32 @cli_ac_addsig(%struct.cli_matcher* nocapture %root, i8* %virname, i8* %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, i8* %offset, i8 zeroext %target) nounwind {
+define i32 @cli_ac_addsig(%struct.cli_matcher* nocapture %root, i8* %virname, i8* %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, i8* %offset, i8 zeroext %target) nounwind {
 entry:
        br i1 undef, label %bb126, label %bb1
 
@@ -65,9 +65,9 @@ bb18:         ; preds = %bb18, %bb.nph
        br i1 undef, label %bb18, label %bb22
 
 bb22:          ; preds = %bb18, %bb17
-       %0 = getelementptr i8* null, i32 10             ; <i8*> [#uses=1]
+       %0 = getelementptr i8, i8* null, i32 10         ; <i8*> [#uses=1]
        %1 = bitcast i8* %0 to i16*             ; <i16*> [#uses=1]
-       %2 = load i16* %1, align 2              ; <i16> [#uses=1]
+       %2 = load i16, i16* %1, align 2         ; <i16> [#uses=1]
        %3 = add i16 %2, 1              ; <i16> [#uses=1]
        %4 = zext i16 %3 to i32         ; <i32> [#uses=1]
        %5 = mul i32 %4, 3              ; <i32> [#uses=1]