The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions

[oota-llvm.git] / test / CodeGen / ARM / 2009-08-15-RegScavenger-EarlyClobber.ll

diff --git a/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll b/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll
index 15fa145c5d922cf639765b2b7b75d736d01d49f9..4b4101556f187ada6fca8c2d40d9d82d7c57c4d0 100644 (file)
--- a/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll
+++ b/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -mtriple=arm-linux-gnueabi
 ; PR4528
 
 ; Inline asm is allowed to contain operands "=&r", "0".
@@ -6,7 +6,7 @@
 %struct.device_dma_parameters = type { i32, i32 }
 %struct.iovec = type { i8*, i32 }
 
-define arm_aapcscc i32 @generic_segment_checks(%struct.iovec* nocapture %iov, i32* nocapture %nr_segs, i32* nocapture %count, i32 %access_flags) nounwind optsize {
+define i32 @generic_segment_checks(%struct.iovec* nocapture %iov, i32* nocapture %nr_segs, i32* nocapture %count, i32 %access_flags) nounwind optsize {
 entry:
   br label %bb8