ARM instructions that are both predicated and set the condition codes

[oota-llvm.git] / test / CodeGen / ARM / 2009-08-15-RegScavengerAssert.ll

diff --git a/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll b/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll
index a46482cc731750d77f6454ebd500eea14a1c321f..299364773f6a44feedc3c88abcd65d811dd10dde 100644 (file)
--- a/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll
+++ b/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll
@@ -1,10 +1,10 @@
-; RUN: llc < %s -march=arm
+; RUN: llc < %s -mtriple=arm-linux-gnueabi
 ; PR4716
 
-define arm_aapcscc void @_start() nounwind naked {
+define void @_start() nounwind naked {
 entry:
-  tail call arm_aapcscc  void @exit(i32 undef) noreturn nounwind
+  tail call  void @exit(i32 undef) noreturn nounwind
   unreachable
 }
 
-declare arm_aapcscc void @exit(i32) noreturn nounwind
+declare void @exit(i32) noreturn nounwind