The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions

[oota-llvm.git] / test / CodeGen / ARM / 2009-10-30.ll

diff --git a/test/CodeGen/ARM/2009-10-30.ll b/test/CodeGen/ARM/2009-10-30.ll
index 82563869bd96866ffec133f8ba888277e8538f55..87d1a8b9e9a2455dfcd5ae0b243520cf41d2d53c 100644 (file)
--- a/test/CodeGen/ARM/2009-10-30.ll
+++ b/test/CodeGen/ARM/2009-10-30.ll
@@ -5,8 +5,8 @@
 define void @f(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, ...) {
 entry:
 ;CHECK: sub    sp, sp, #4
-;CHECK: add    r0, sp, #8
-;CHECK: str    r0, [sp], #+4
+;CHECK: add    r{{[0-9]+}}, sp, #8
+;CHECK: str    r{{[0-9]+}}, [sp], #4
 ;CHECK: bx     lr
        %ap = alloca i8*, align 4
        %ap1 = bitcast i8** %ap to i8*