ARM: Fast-isel register class constrain for extends.

[oota-llvm.git] / test / CodeGen / ARM / 2009-10-30.ll

diff --git a/test/CodeGen/ARM/2009-10-30.ll b/test/CodeGen/ARM/2009-10-30.ll
index 90a5bd2a75798c2eb38d1da4b41bc4ace2cd59b8..e46ab1eb2ab938a10802802a512244fb9049244a 100644 (file)
--- a/test/CodeGen/ARM/2009-10-30.ll
+++ b/test/CodeGen/ARM/2009-10-30.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s  -mtriple=arm-linux-gnueabi  | FileCheck %s
+; RUN: llc < %s  -mtriple=armv6-linux-gnueabi  | FileCheck %s
 ; This test checks that the address of the varg arguments is correctly
 ; computed when there are 5 or more regular arguments.
 
@@ -6,7 +6,7 @@ define void @f(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, ...) {
 entry:
 ;CHECK: sub    sp, sp, #4
 ;CHECK: add    r{{[0-9]+}}, sp, #8
-;CHECK: str    r{{[0-9]+}}, [sp], #+4
+;CHECK: str    r{{[0-9]+}}, [sp], #4
 ;CHECK: bx     lr
        %ap = alloca i8*, align 4
        %ap1 = bitcast i8** %ap to i8*