The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions

[oota-llvm.git] / test / CodeGen / ARM / bits.ll

diff --git a/test/CodeGen/ARM/bits.ll b/test/CodeGen/ARM/bits.ll
index 0ac4f9a3833dc1fd7ec910552bcab809364338f6..ce1b2ad5fad3ba42ce8f6f4a20a88c99b2c1fcf4 100644 (file)
--- a/test/CodeGen/ARM/bits.ll
+++ b/test/CodeGen/ARM/bits.ll
@@ -1,36 +1,41 @@
-; RUN: llvm-as < %s | llc -march=arm > %t
-; RUN: grep and      %t | count 1
-; RUN: grep orr      %t | count 1
-; RUN: grep eor      %t | count 1
-; RUN: grep mov.*lsl %t | count 1
-; RUN: grep mov.*asr %t | count 1
+; RUN: llc < %s -march=arm | FileCheck %s
 
 define i32 @f1(i32 %a, i32 %b) {
 entry:
+; CHECK: f1
+; CHECK: and r0, r1, r0
        %tmp2 = and i32 %b, %a          ; <i32> [#uses=1]
        ret i32 %tmp2
 }
 
 define i32 @f2(i32 %a, i32 %b) {
 entry:
+; CHECK: f2
+; CHECK: orr r0, r1, r0
        %tmp2 = or i32 %b, %a           ; <i32> [#uses=1]
        ret i32 %tmp2
 }
 
 define i32 @f3(i32 %a, i32 %b) {
 entry:
+; CHECK: f3
+; CHECK: eor r0, r1, r0
        %tmp2 = xor i32 %b, %a          ; <i32> [#uses=1]
        ret i32 %tmp2
 }
 
 define i32 @f4(i32 %a, i32 %b) {
 entry:
+; CHECK: f4
+; CHECK: lsl
        %tmp3 = shl i32 %a, %b          ; <i32> [#uses=1]
        ret i32 %tmp3
 }
 
 define i32 @f5(i32 %a, i32 %b) {
 entry:
+; CHECK: f5
+; CHECK: asr
        %tmp3 = ashr i32 %a, %b         ; <i32> [#uses=1]
        ret i32 %tmp3
 }