The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions

[oota-llvm.git] / test / CodeGen / ARM / carry.ll

diff --git a/test/CodeGen/ARM/carry.ll b/test/CodeGen/ARM/carry.ll
index 294de5ff727805d945386d331f7f500d1ba59a02..a6a7ed6af1840efbd3d767b49d3b95b3579519ec 100644 (file)
--- a/test/CodeGen/ARM/carry.ll
+++ b/test/CodeGen/ARM/carry.ll
@@ -1,14 +1,19 @@
-; RUN: llc < %s -march=arm | grep "subs r" | count 2
-; RUN: llc < %s -march=arm | grep "adc r"
-; RUN: llc < %s -march=arm | grep "sbc r"  | count 2
+; RUN: llc < %s -march=arm | FileCheck %s
 
 define i64 @f1(i64 %a, i64 %b) {
+; CHECK: f1:
+; CHECK: subs r
+; CHECK: sbc r
 entry:
        %tmp = sub i64 %a, %b
        ret i64 %tmp
 }
 
 define i64 @f2(i64 %a, i64 %b) {
+; CHECK: f2:
+; CHECK: adc r
+; CHECK: subs r
+; CHECK: sbc r
 entry:
         %tmp1 = shl i64 %a, 1
        %tmp2 = sub i64 %tmp1, %b