define i64 @f3(i32 %al, i32 %bl) {
; CHECK: f3:
; CHECK: adds r
-; CHECK: adcs r
; CHECK: adc r
entry:
; unsigned wide add
%dw = add i64 %ch, %bw
ret i64 %dw
}
+
+; rdar://10073745
+define i64 @f4(i64 %x) nounwind readnone {
+entry:
+; CHECK: f4:
+; CHECK: rsbs r
+; CHECK: rsc r
+ %0 = sub nsw i64 0, %x
+ ret i64 %0
+}